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Am29LV2562M
Data Sheet
July 2003 The following document specifies Spansion memory products that are now offered by both Advanced Micro Devices and Fujitsu. Although the document is marked with the name of the company that originally developed the specification, these products will be offered to customers of both AMD and Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a Spansion product. Any changes that have been made are the result of normal datasheet improvement and are noted in the document revision summary, where supported. Future routine revisions will occur when appropriate, and changes will be noted in a revision summary.
Continuity of Ordering Part Numbers
AMD and Fujitsu continue to support existing part numbers beginning with "Am" and "MBM". To order these products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about Spansion memory solutions.
Publication Number 26494 Revision B
Amendment +1
Issue Date October 9, 2003
THIS PAGE LEFT INTENTIONALLY BLANK.
PRELIMINARY
Am29LV2562M
512 Megabit (16 M x 32-Bit/32 M x 16-Bit) MirrorBitTM 3.0 Volt-only Uniform Sector Flash Memory with VersatileI/OTM Control
DISTINCTIVE CHARACTERISTICS
ARCHITECTURAL ADVANTAGES Single power supply operation -- 3 volt read, erase, and program operations VersatileI/OTM control -- Device generates data output voltages and tolerates data input voltages on the CE# and DQ inputs/outputs as determined by the voltage on the VIO pin; operates from 1.65 to 3.6 V Manufactured on 0.23 m MirrorBit process technology
TM
-- 4-doubleword/8-word page read buffer -- 16-doubleword/32-word write buffer Low power consumption (typical values at 3.0 V, 5 MHz) -- 26 mA typical active read current -- 100 mA typical erase/program current -- 2 A typical standby mode current Package options -- 80-ball Fortified BGA SOFTWARE & HARDWARE FEATURES Software features -- Program Suspend & Resume: read other sectors before programming operation is completed -- Erase Suspend & Resume: read/program other sectors before an erase operation is completed -- Data# polling & toggle bits provide status -- Unlock Bypass Program command reduces overall multiple-word or byte programming time -- CFI (Common Flash Interface) compliant: allows host system to identify and accommodate multiple flash devices Hardware features -- Sector Group Protection: hardware-level method of preventing write operations within a sector group -- Temporary Sector Group Unprotect: VID-level method of changing code in locked sector groups -- WP#/ACC input accelerates programming time (when high voltage is applied) for greater throughput during system production. Protects first or last sector regardless of sector protection settings -- Hardware reset input (RESET#) resets device -- Ready/Busy# output (RY/BY#) detects program or erase cycle completion
SecSiTM (Secured Silicon) Sector region -- 128-doubleword/256-word sector for permanent, secure identification through an 8-doubleword/16-word random Electronic Serial Number, accessible through a command sequence -- May be programmed and locked at the factory or by the customer Flexible sector architecture -- Five hundred twelve 32 Kdoubleword (64 Kword) sectors Compatibility with JEDEC standards -- Provides pinout and software compatibility for single-power supply flash, and superior inadvertent write protection 100,000 erase cycles per sector 20-year data retention at 125C PERFORMANCE CHARACTERISTICS High performance -- 120 ns access time -- 30 ns page read times -- 0.5 s typical sector erase time -- 15 s typical write buffer doubleword programming time: 16-doubleword/32-word write buffer reduces overall programming time for multiple-word updates
This Data Sheet states AMD's current technical specifications regarding the Products described herein. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
Publication# 26494 Rev: B Amendment/+1 Issue Date: October 9, 2003
Refer to AMD's Website (www.amd.com) for the latest information.
PRELIMINARY
GENERAL DESCRIPTION
The Am29LV2562M consists of two 256 Mbit, 3.0 volt single power supply flash memory devices and is organized as 16,777,216 doublewords or 33,554,432 words. The device has a 32-bit wide data bus that can also function as an 16-bit wide data bus by using the WORD# input. The device can be programmed either in the host system or in standard EPROM programmers. An access time of 120 ns is available. Note that each access time has a specific operating voltage range (VCC) as specified in the Product Selector Guide and the Ordering Information sections. The device is offered in an 80-ball Fortified BGA package. Each device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls. Each device requires only a single 3.0 volt power supply for both read and write functions. In addition to a V CC input, a high-voltage accelerated program (WP#/ACC) input provides shorter programming times through increased current. This feature is intended to facilitate factory throughput during system production, but may also be used in the field if desired. The device is entirely command set compatible with the JEDEC single-power-supply Flash standard. Commands are written to the device using standard microprocessor write timing. Write cycles also internally latch addresses and data needed for the programming and erase operations. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Device programming and erasure are initiated through command sequences. Once a program or erase operation has begun, the host system need only poll the DQ7 and DQ15 (Data# Polling) or DQ6 and DQ14 (toggle) status bits or monitor the Ready/Busy# (RY/BY#) outputs to determine whether the operation is complete. To facilitate programming, an Unlock Bypass mode reduces command sequence overhead by requiring only two write cycles to program data instead of four. The VersatileI/OTM (VIO) control allows the host system to set the voltage levels that the device generates and tolerates on the CE# control input and DQ I/Os to the same voltage level that is asserted on the VIO pin. Refer to the Ordering Information section for valid VIO options. Hardware data protection measures include a low V CC detector that automatically inhibits write operations during power transitions. The hardware sector group protection feature disables both program and erase operations in any combination of sector groups of memory. This can be achieved in-system or via programming equipment. The Erase Suspend/Erase Resume feature allows the host system to pause an erase operation in a given sector to read or program any other sector and then complete the erase operation. The Program Suspend/Program Resume feature enables the host system to pause a program operation in a given sector to read any other sector and then complete the program operation. The hardware RESET# pin terminates any operation in progress and resets the device, after which it is then ready for a new operation. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the host system to read boot-up firmware from the Flash memory device. The device reduces power consumption in the standby mode when it detects specific voltage levels on CE# and RESET#, or when addresses have been stable for a specified period of time. The SecSiTM (Secured Silicon) Sector provides a 128-doubleword/256-word area for code or data that can be permanently protected. Once this sector is protected, no further changes within the sector can occur. The Write Protect (WP#/ACC) feature protects the first or last sector by asserting a logic low on the WP# pin. AMD MirrorBitTM flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a sector simultaneously via hot-hole assisted erase. The data is programmed using hot electron injection.
RELATED DOCUMENTS
For a comprehensive information on MirrorBit products, including migration information, data sheets, application notes, and software drivers, please see www.amd.comFlash MemoryProduct InformationMirrorBitFlash InformationTechnical Documentation. The following is a partial list of documents closely related to this product: MirrorBitTM Flash Memory Write Buffer Programming and Page Buffer Read Implementing a Common Layout for AMD MirrorBit and Intel StrataFlash Memory Devices Migrating from Single-byte to Three-byte Device IDs
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PRELIMINARY
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4 MCP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 4 Special Package Handling Instructions .................................... 6 Logic Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 x16 Mode .................................................................................. 7 x32 Mode .................................................................................. 7
Table 1. Device Bus Operations ....................................................... 9
Chip Erase Command Sequence ........................................... 38 Sector Erase Command Sequence ........................................ 38
Figure 7. Erase Operation .............................................................. 39
Erase Suspend/Erase Resume Commands ........................... 39 DQ7 and DQ5: Data# Polling .................................................. 43
Figure 7. Data# Polling Algorithm .................................................. 43
DQ6 and DQ14: Toggle Bits I ................................................. 44
Figure 8. Toggle Bit Algorithm ........................................................ 45
VersatileIOTM (VIO) Control ........................................................ 9 Requirements for Reading Array Data ................................... 10
Page Mode Read ............................................................................10
Writing Commands/Command Sequences ............................ 10
Write Buffer .....................................................................................10 Accelerated Program Operation ......................................................10 Autoselect Functions .......................................................................10
DQ2 and DQ10: Toggle Bits II ................................................ 45 Reading Toggle Bits DQ6 and DQ14/DQ2 and DQ10 ............ 45 DQ5 and DQ13: Exceeded Timing Limits ............................... 46 DQ3 and DQ11: Sector Erase Timer ...................................... 46 DQ1: Write-to-Buffer Abort ..................................................... 47
Table 12. Write Operation Status................................................... 47 Figure 9. Maximum Negative Overshoot Waveform ..................... 48 Figure 10. Maximum Positive Overshoot Waveform ..................... 48 Figure 11. Test Setup ..................................................................... 50 Table 13. Test Specifications ......................................................... 50
Automatic Sleep Mode ........................................................... 11 RESET#: Hardware Reset Pin ............................................... 11 Output Disable Mode .............................................................. 11
Table 2. Sector Address Table........................................................ 12 Table 3. Autoselect Codes, (High Voltage Method) ....................... 23
Key to Switching Waveforms. . . . . . . . . . . . . . . . 50
Figure 12. Input Waveforms and Measurement Levels ...................................................................... 50
Sector Group Protection and Unprotection ............................. 24
Table 4. Sector Group Protection/Unprotection Address Table ..... 24
Temporary Sector Group Unprotect ....................................... 26
Figure 1. Temporary Sector Group Unprotect Operation ................26 Figure 2. In-System Sector Group Protect/Unprotect Algorithms ...27
Read-Only Operations ........................................................... 51
Figure 13. Read Operation Timings ............................................... 51 Figure 14. Page Read Timings ...................................................... 52
SecSi (Secured Silicon) Sector Flash Memory Region .......... 28
Table 5. SecSi Sector Contents ...................................................... 28 Figure 3. SecSi Sector Protect Verify ..............................................29
Hardware Reset (RESET#) .................................................... 53
Figure 15. Reset Timings ............................................................... 53
Erase and Program Operations .............................................. 54
Figure 16. Program Operation Timings .......................................... 55 Figure 17. Accelerated Program Timing Diagram .......................... 55 Figure 18. Chip/Sector Erase Operation Timings .......................... 56 Figure 19. Data# Polling Timings (During Embedded Algorithms) . 57 Figure 20. Toggle Bit Timings (During Embedded Algorithms) ...... 58 Figure 21. DQ2 vs. DQ6 ................................................................. 58
Hardware Data Protection ...................................................... 29
Low VCC Write Inhibit .....................................................................29 Write Pulse "Glitch" Protection ........................................................29 Logical Inhibit ..................................................................................29 Power-Up Write Inhibit ....................................................................29
Common Flash Memory Interface (CFI) . . . . . . . 29 Reading Array Data ................................................................ 33 Reset Command ..................................................................... 33 Autoselect Command Sequence ............................................ 33 Enter SecSi Sector/Exit SecSi Sector Command Sequence .. 34 Doubleword/Word Program Command Sequence ................. 34
Unlock Bypass Command Sequence ..............................................34 Write Buffer Programming ...............................................................34 Accelerated Program ......................................................................35 Figure 4. Write Buffer Programming Operation ...............................36 Figure 5. Program Operation ..........................................................37
Temporary Sector Unprotect .................................................. 59
Figure 22. Temporary Sector Group Unprotect Timing Diagram ... 59 Figure 23. Sector Group Protect and Unprotect Timing Diagram .. 60
Alternate CE# Controlled Erase and Program Operations ..... 61
Figure 24. Alternate CE# Controlled Write (Erase/Program) Operation Timings .......................................................................... 62
Program Suspend/Program Resume Command Sequence ... 37
Figure 6. Program Suspend/Program Resume ...............................38
Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 62 Erase And Programming Performance. . . . . . . . 63 TSOP Pin and BGA Package Capacitance . . . . . 63 Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 LSC080-80-Ball Fortified Ball Grid Array 18 x 12 mm Package .............................................................. 64
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PRELIMINARY
PRODUCT SELECTOR GUIDE
Part Number Speed Option Max. Access Time (ns) Max. CE# Access Time (ns) Max. Page access time (tPACC) Max. OE# Access Time (ns) VCC = 3.0-3.6 V, VIO = 1.65-3.6V 120 120 30 30 Am29LV2562M 120R
MCP BLOCK DIAGRAM
A23 to A0 RY/BY# CE# OE# WE# RESET# WORD# WP#/ACC 256 Mbit Flash Memory #1
DQ23/A-1 to DQ16; DQ7-DQ0 X16
X32
DQ31 to DQ0
256 Mbit Flash Memory #2
X16 DQ32/A-1 to DQ24; DQ15 TO DQ8
Note:In x16 Mode, DQ31 and DQ23 must be connected together on the board.
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PRELIMINARY
FLASH MEMORY BLOCK DIAGRAM
RY/BY# VCC VSS Erase Voltage Generator VIO Input/Output Buffers Sector Switches DQ31-DQ0 (A-1)
RESET# WE# WP#/ACC WORD#
State Control Command Register
PGM Voltage Generator Chip Enable Output Enable Logic STB Data Latch
CE# OE#
STB VCC Detector Timer Address Latch
Y-Decoder
Y-Gating
X-Decoder
Cell Matrix
A23-A0
Note:In x16 Mode, DQ31 and DQ23 must be connected together on the board.
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PRELIMINARY
CONNECTION DIAGRAMS
80-ball Fortified BGA Top View, Balls Facing Down
A8 DQ21 A7 DQ23/A-1 A6 DQ30 A5 VSS A4 VCC A3 DQ31/A-1 A2 DQ18 A1 RFU
B8 DQ28 B7 A13 B6 A9 B5 WE# B4
C8 A22 C7 A12 C6 A8 C5 RESET# C4
D8 A23 D7 A14 D6 A10 D5 A21 D4 A18 D3 A6 D2 A2 D1 RFU
E8 VIO E7 A15 E6 A11 E5 A19 E4 A20 E3 A5 E2 A1 E1 RFU
F8 VSS F7 A16 F6 DQ7 F5 DQ5 F4 DQ2 F3 DQ0 F2 A0 F1 RFU
G8 RFU G7 WORD# G6 DQ14 G5 DQ12 G4 DQ10 G3 DQ8 G2 CE# G1 VIO
H8 RFU H7 DQ15 H6 DQ13 H5 VCC H4 DQ11 H3 DQ9 H2 OE# H1 RFU
J8 DQ29 J7 VSS J6 DQ6 J5 DQ4 J4 DQ3 J3 DQ1 J2 VSS J1 DQ24
K8 DQ22 K7 DQ20 K6 DQ27 K5 DQ26 K4 DQ19 K3 DQ17 K2 VCC K1 DQ25
RY/BY# WP#/ACC B3 A7 B2 A3 B1 DQ16 C3 A17 C2 A4 C1 VCC
Note: The FBGA package pinout configuration shown is preliminary. The ball count and package physical dimensions have not yet been determined. Contact AMD for further information.
Special Package Handling Instructions
Special handling is required for Flash Memory products in molded packages (BGA). The package and/or data integrity may be compromised if the package body is
exposed to temperatures above 150C for prolonged periods of time.
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PRELIMINARY
PIN CONFIGURATION
A-1
= Least significant address bit for the 16-bit data bus, and selects between the high and low word. A -1 is not used for the 32-bit mode (WORD# = VIH). = 24-bit address bus for 512 Mb device. = 32-bit data inputs/outputs/float = Selects 16-bit or 32-bit mode. When WORD# = VIH, data is output on DQ31-DQ0. When WORD# = VIL, data is output on DQ15-DQ0. = Chip Enable Input. = Output Enable Input. = Write enable. VSS RY/BY# = Device ground = Ready/Busy output and open drain. When RY/BY# = VOH, the device is ready to accept read operations and commands. When RY/BY# = VOL, the device is either executing an embedded algorithm or the device is executing a hardware reset operation.
A23-A0 DQ31-DQ0 WORD#
WP#/ACC VCC RESET# NC
= Write Protect input/Acceleration input. = Power Supply (2.7 V to 3.6 V) = Hardware reset input = Pin not connected internally
CE# OE# WE#
LOGIC SYMBOLS x16 Mode
25 A23 to A-1 CE# OE# WE# WP#/ACC RESET# WORD# VIO RY/BY# DQ15-DQ0 CE# OE# WE# WP#/ACC RESET# WORD# VIO RY/BY# 16
x32 Mode
24 A23-A0 DQ31-DQ0 32
Note:In x16 Mode, DQ31 and DQ23 must be connected together on the board.
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PRELIMINARY
ORDERING INFORMATION Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the following:
Am29LV2562M
H
120R
PI
I
TEMPERATURE RANGE I = Industrial (-40C to +85C) PACKAGE TYPE PI = 80-Ball Fortified Ball Grid Array (FBGA), 18 x 12 mm, (LSC080) SPEED OPTION See Product Selector Guide and Valid Combinations SECTOR ARCHITECTURE AND SECTOR WRITE PROTECTION (WP# = VIL) H = Uniform sector device, highest address sector protected L = Uniform sector device, lowest address sector protected
DEVICE NUMBER/DESCRIPTION Am29LV2562MH/L 2 x 256 Megabit (16 M x 32-Bit/32 M x 16-Bit) MirrorBitTM Uniform Sector Flash Memory 3.0 Volt-only Read, Program, and Erase
Valid Combinations
Valid Combinations for Fortified BGA Package Order Number Package Marking Am29LV2562MH120R, L2562MH12RI PII Am29LV2562ML120R L2562ML12RI VIO Speed VCC (ns) Range Range 120 3.0- 3.6 V 1.65- 3.6 V
Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations.
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PRELIMINARY
DEVICE BUS OPERATIONS
This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory location. The register is a latch used to store the commands, along with the address and data information needed to execute the command. The contents of the Table 1. register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. Table 1 lists the device bus operations, the inputs and control levels they require, and the resulting output. The following subsections describe each of these operations in further detail.
Device Bus Operations
DQ31-DQ16
Operation Read Write (Program/Erase) Accelerated Program Standby Output Disable Reset Sector Group Protect (Note 2) Sector Group Unprotect (Note 2) Temporary Sector Group Unprotect
CE# L L L VCC 0.3 V L X L
OE# L H H X H X H
WE# H L L X H X L
RESET# H H H VCC 0.3 V H L VID
WP#
ACC
Addresses (Note 2) AIN AIN AIN X X X SA, A6 =L, A3=L, A2=L, A1=H, A0=L SA, A6=H, A3=L, A2=L, A1=H, A0=L AIN
DQ15- DQ0 DOUT
WORD# = VIH DOUT
WORD# = VIL
X (Note 3) (Note 3) X X X H
L/H L/H VHH H L/H L/H L/H
DQ31-DQ16 = High-Z, (Note 4) (Note 4) DQ31 & (Note 4) (Note 4) DQ23= A-1 High-Z High-Z High-Z (Note 4) High-Z High-Z High-Z X High-Z High-Z High-Z X
L
H
L
VID
H
L/H
(Note 4)
X
X
X
X
X
VID
H
L/H
(Note 4) (Note 4)
High-Z
Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 11.5-12.5 V, VHH = 11.5-12.5V, X = Don't Care, SA = Sector Address, AIN = Address In, DIN = Data In, DOUT = Data Out Notes:
1. Addresses are A23:A0 in doubleword mode; A23:A-1 in word mode. Sector addresses are A23:A15 in both modes. 2. The sector group protect and sector group unprotect functions may also be implemented via programming equipment. See the "Sector Group Protection and Unprotection" section. 3. If WP# = VIL, the first or last sector group remains protected. If WP# = VIH, the first or last sector will be protected or unprotected as determined by the method described in "Write Protect (WP#)" All sectors are unprotected when shipped from the factory (The SecSi Sector may be factory protected depending on version ordered.) 4. DIN or DOUT as required by command sequence, data polling, or sector protect algorithm (see Figure 2).
Word/Byte Configuration
The WORD# pin controls whether the device data I/O pins operate in the word or doubleword configuration. If the WORD# pin is set at VIH, the device is in doubleword configuration, DQ31-DQ0 are active and controlled by CE# and OE#. If the WORD# pin is set at VIL , the device is in word configuration, and only data I/O pins DQ15-DQ0 are active and controlled by CE# and OE#. The data I/O pins DQ31-DQ16 are tri-stated, and the DQ23 and
DQ31 pins are used as inputs for the LSB (A-1) address function.
VersatileIOTM (VIO) Control
The VersatileIOTM (VIO) control allows the host system to set the voltage levels that the device generates and tolerates on CE# and DQ I/Os to the same voltage level that is asserted on VIO. See Ordering Information for VIO options on this device.
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PRELIMINARY
Requirements for Reading Array Data
To read array data from the outputs, the system must drive the CE# and OE# pins to VIL. CE# is the power control and selects the device. OE# is the output control and gates array data to the output pins. WE# should remain at VIH. The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. The device remains enabled for read access until the command register contents are altered. See "Reading Array Data" for more information. Refer to the AC Read-Only Operations table for timing specifications and to Figure 13 for the timing diagram. Refer to the DC Characteristics table for the active current specification on reading array data. Page Mode Read The device is capable of fast page mode read and is compatible with the page mode Mask ROM read operation. This mode provides faster read access speed for random locations within a page. The page size of the device is 4 doublewords/8 words. The appropriate page is selected by the higher address bits A(max)-A2. Address bits A1-A0 in doubleword mode (A1-A-1 in word mode) determine the specific word within a page. This is an asynchronous operation; the microprocessor supplies the specific word location. The random or initial page access is equal to tACC or tCE and subsequent page read accesses (as long as the locations specified by the microprocessor falls within that page) is equivalent to tPACC. When CE# is deasserted and reasserted for a subsequent access, the access time is t ACC or t CE . Fast page mode accesses are obtained by keeping the "read-page addresses" constant and changing the "intra-read page" addresses.
using both standard and Unlock Bypass command sequences. An erase operation can erase one sector, multiple sectors, or the entire device. Table 2 indicates the address space that each sector occupies. Refer to the DC Characteristics table for the active current specification for the write mode. The AC Characteristics section contains timing specification tables and timing diagrams for write operations. Write Buffer Write Buffer Programming allows the system write to a maximum of 16 doublewords/32 words in one programming operation. This results in faster effective programming time than the standard programming algorithms. See "Write Buffer" for more information. Accelerated Program Operation The device offers accelerated program operations through the ACC function. This is one of two functions provided by the WP#/ACC pin. This function is primarily intended to allow faster manufacturing throughput at the factory. If the system asserts VHH on this pin, the device automatically enters the aforementioned Unlock Bypass mode, temporarily unprotects any protected sector groups, and uses the higher voltage on the pin to reduce the time required for program operations. The system would use a two-cycle program command sequence as required by the Unlock Bypass mode. Removing VHH from the WP#/ACC pin returns the device to normal operation. Note that the WP#/ACC pin must not be at V HH for operations other than accelerated programming, or device damage may result. WP# has an internal pullup; when unconnected, WP# is at VIH. Autoselect Functions If the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal register (which is separate from the memory array) on DQ7-DQ0. Standard read cycle timings apply in this mode. Refer to the Autoselect Mode and Autoselect Command Sequence sections for more information.
Writing Commands/Command Sequences
To write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive WE# and CE# to VIL, and OE# to VIH. The device features an Unlock Bypass mode to facilitate faster programming. Once the device enters the Unlock Bypass mode, only two write cycles are required to program a word or byte, instead of four. The "Doubleword/Word Program Command Sequence" section has details on programming data to the device
Standby Mode
When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input. The device enters the CMOS standby mode when the CE# and RESET# pins are both held at VCC 0.3 V. (Note that this is a more restricted voltage range than
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PRELIMINARY VIH.) If CE# and RESET# are held at VIH, but not within VCC 0.3 V, the device will be in the standby mode, but the standby current will be greater. The device requires standard access time (t CE ) for read access when the device is in either of these standby modes, before it is ready to read data. If the device is deselected during erasure or programming, the device draws active current until the operation is completed. Refer to the DC Characteristics table for the standby current specification. SET# pin is driven low for at least a period of tRP, the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity. Current is reduced for the duration of the RESET# pulse. When RESET# is held at VSS0.3 V, the device draws CMOS standby current (ICC4). If RESET# is held at VIL but not within VSS0.3 V, the standby current will be greater. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory. Refer to the AC Characteristics tables for RESET# parameters and to Figure 15 for the timing diagram.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables this mode when addresses remain stable for t ACC + 30 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. Refer to the DC Characteristics table for the automatic sleep mode current specification.
Output Disable Mode
When the OE# input is at VIH, output from the device is disabled. The output pins are placed in the high impedance state.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of resetting the device to reading array data. When the RE-
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PRELIMINARY Table 2. Sector Address Table
Sector Size (Kwords/Kdoublewords) 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 16-bit Address Range (in hexadecimal) 0000000-000FFFF 0010000-001FFFF 0020000-002FFFF 0030000-003FFFF 0040000-004FFFF 0050000-005FFFF 0060000-006FFFF 0070000-007FFFF 0080000-008FFFF 0090000-009FFFF 00A0000-00AFFFF 00B0000-00BFFFF 00C0000-00CFFFF 00D0000-00DFFFF 00E0000-00EFFFF 00F0000-00FFFFF 0100000-010FFFF 0110000-011FFFF 0120000-012FFFF 0130000-013FFFF 0140000-014FFFF 0150000-015FFFF 0160000-016FFFF 0170000-017FFFF 0180000-018FFFF 0190000-019FFFF 01A0000-01AFFFF 01B0000-01BFFFF 01C0000-01CFFFF 01D0000-01DFFFF 01E0000-01EFFFF 01F0000-01FFFFF 0200000-020FFFF 0210000-021FFFF 0220000-022FFFF 0230000-023FFFF 0240000-024FFFF 0250000-025FFFF 0260000-026FFFF 0270000-027FFFF 0280000-028FFFF 0290000-029FFFF 02A0000-02AFFFF 02B0000-02BFFFF 02C0000-02CFFFF 02D0000-02DFFFF 02E0000-02EFFFF 32-bit Address Range (in hexadecimal) 000000-007FFF 008000-00FFFF 010000-017FFF 018000-01FFFF 020000-027FFF 028000-02FFFF 030000-037FFF 038000-03FFFF 040000-047FFF 048000-04FFFF 050000-057FFF 058000-05FFFF 060000-067FFF 068000-06FFFF 070000-077FFF 078000-07FFFF 080000-087FFF 088000-08FFFF 090000-097FFF 098000-09FFFF 0A0000-0A7FFF 0A8000-0AFFFF 0B0000-0B7FFF 0B8000-0BFFFF 0C0000-0C7FFF 0C8000-0CFFFF 0D0000-0D7FFF 0D8000-0DFFFF 0E0000-0E7FFF 0E8000-0EFFFF 0F0000-0F7FFF 0F8000-0FFFFF 100000-107FFF 108000-10FFFF 110000-117FFF 118000-11FFFF 120000-127FFF 128000-12FFFF 130000-137FFF 138000-13FFFF 140000-147FFF 148000-14FFFF 150000-157FFF 158000-15FFFF 160000-167FFF 168000-16FFFF 170000-177FFF
Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38 SA39 SA40 SA41 SA42 SA43 SA44 SA45 SA46 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
A23-A15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12
Am29LV2562M
October 9, 2003
PRELIMINARY Table 2. Sector Address Table (Continued)
Sector Size (Kwords/Kdoublewords) 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 16-bit Address Range (in hexadecimal) 02F0000-02FFFFF 0300000-030FFFF 0310000-031FFFF 0320000-032FFFF 0330000-033FFFF 0340000-034FFFF 0350000-035FFFF 0360000-036FFFF 0370000-037FFFF 0380000-038FFFF 0390000-039FFFF 03A0000-03AFFFF 03B0000-03BFFFF 03C0000-03CFFFF 03D0000-03DFFFF 03E0000-03EFFFF 03F0000-03FFFFF 0400000-040FFFF 0410000-041FFFF 0420000-042FFFF 0430000-043FFFF 0440000-044FFFF 0450000-045FFFF 0460000-046FFFF 0470000-047FFFF 0480000-048FFFF 0490000-049FFFF 04A0000-04AFFFF 04B0000-04BFFFF 04C0000-04CFFFF 04D0000-04DFFFF 04E0000-04EFFFF 04F0000-04FFFFF 0500000-050FFFF 0510000-051FFFF 0520000-052FFFF 0530000-053FFFF 0540000-054FFFF 0550000-055FFFF 0560000-056FFFF 0570000-057FFFF 0580000-058FFFF 0590000-059FFFF 05A0000-05AFFFF 05B0000-05BFFFF 05C0000-05CFFFF 05D0000-05DFFFF 05E0000-05EFFFF 32-bit Address Range (in hexadecimal) 178000-17FFFF 180000-187FFF 188000-18FFFF 190000-197FFF 198000-19FFFF 1A0000-1A7FFF 1A8000-1AFFFF 1B0000-1B7FFF 1B8000-1BFFFF 1C0000-1C7FFF 1C8000-1CFFFF 1D0000-1D7FFF 1D8000-1DFFFF 1E0000-1E7FFF 1E8000-1EFFFF 1F0000-1F7FFF 1F8000-1FFFFF 200000-207FFF 208000-20FFFF 210000-217FFF 218000-21FFFF 220000-227FFF 228000-22FFFF 230000-237FFF 238000-23FFFF 240000-247FFF 248000-24FFFF 250000-257FFF 258000-25FFFF 260000-267FFF 268000-26FFFF 270000-277FFF 278000-27FFFF 280000-287FFF 288000-28FFFF 290000-297FFF 298000-29FFFF 2A0000-2A7FFF 2A8000-2AFFFF 2B0000-2B7FFF 2B8000-2BFFFF 2C0000-2C7FFF 2C8000-2CFFFF 2D0000-2D7FFF 2D8000-2DFFFF 2E0000-2E7FFF 2E8000-2EFFFF 2F0000-2F7FFF
Sector SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70 SA71 SA72 SA73 SA74 SA75 SA76 SA77 SA78 SA79 SA80 SA81 SA82 SA83 SA84 SA85 SA86 SA87 SA88 SA89 SA90 SA91 SA92 SA93 SA94 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
A23-A15 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
October 9, 2003
Am29LV2562M
13
PRELIMINARY Table 2. Sector Address Table (Continued)
Sector Size (Kwords/Kdoublewords) 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 16-bit Address Range (in hexadecimal) 05F0000-05FFFFF 0600000-060FFFF 0610000-061FFFF 0620000-062FFFF 0630000-063FFFF 0640000-064FFFF 0650000-065FFFF 0660000-066FFFF 0670000-067FFFF 0680000-068FFFF 0690000-069FFFF 06A0000-06AFFFF 06B0000-06BFFFF 06C0000-06CFFFF 06D0000-06DFFFF 06E0000-06EFFFF 06F0000-06FFFFF 0700000-070FFFF 0710000-071FFFF 0720000-072FFFF 0730000-073FFFF 0740000-074FFFF 0750000-075FFFF 0760000-076FFFF 0770000-077FFFF 0780000-078FFFF 0790000-079FFFF 07A0000-07AFFFF 07B0000-07BFFFF 07C0000-07CFFFF 07D0000-07DFFFF 07E0000-07EFFFF 07F0000-07FFFFF 0800000-080FFFF 0810000-081FFFF 0820000-082FFFF 0830000-083FFFF 0840000-084FFFF 0850000-085FFFF 0860000-086FFFF 0870000-087FFFF 0880000-088FFFF 0890000-089FFFF 08A0000-08AFFFF 08B0000-08BFFFF 08C0000-08CFFFF 08D0000-08DFFFF 08E0000-08EFFFF 32-bit Address Range (in hexadecimal) 2F8000-2FFFFF 300000-307FFF 308000-30FFFF 310000-317FFF 318000-31FFFF 320000-327FFF 328000-32FFFF 330000-337FFF 338000-33FFFF 340000-347FFF 348000-34FFFF 350000-357FFF 358000-35FFFF 360000-367FFF 368000-36FFFF 370000-377FFF 378000-37FFFF 380000-387FFF 388000-38FFFF 390000-397FFF 398000-39FFFF 3A0000-3A7FFF 3A8000-3AFFFF 3B0000-3B7FFF 3B8000-3BFFFF 3C0000-3C7FFF 3C8000-3CFFFF 3D0000-3D7FFF 3D8000-3DFFFF 3E0000-3E7FFF 3E8000-3EFFFF 3F0000-3F7FFF 3F8000-3FFFFF 400000-407FFF 408000-40FFFF 410000-417FFF 418000-41FFFF 420000-427FFF 428000-42FFFF 430000-437FFF 438000-43FFFF 440000-447FFF 448000-44FFFF 450000-457FFF 458000-45FFFF 460000-467FFF 468000-46FFFF 470000-477FFF
Sector SA95 SA96 SA97 SA98 SA99 SA100 SA101 SA102 SA103 SA104 SA105 SA106 SA107 SA108 SA109 SA110 SA111 SA112 SA113 SA114 SA115 SA116 SA117 SA118 SA119 SA120 SA121 SA122 SA123 SA124 SA125 SA126 SA127 SA128 SA129 SA130 SA131 SA132 SA133 SA134 SA135 SA136 SA137 SA138 SA139 SA140 SA141 SA142 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
A23-A15 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
14
Am29LV2562M
October 9, 2003
PRELIMINARY Table 2. Sector Address Table (Continued)
Sector Size (Kwords/Kdoublewords) 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 16-bit Address Range (in hexadecimal) 08F0000-08FFFFF 0900000-090FFFF 0910000-091FFFF 0920000-092FFFF 0930000-093FFFF 0940000-094FFFF 0950000-095FFFF 0960000-096FFFF 0970000-097FFFF 0980000-098FFFF 0990000-099FFFF 09A0000-09AFFFF 09B0000-09BFFFF 09C0000-09CFFFF 09D0000-09DFFFF 09E0000-09EFFFF 09F0000-09FFFFF 0A00000-0A0FFFF 0A10000-0A1FFFF 0A20000-0A2FFFF 0A30000-0A3FFFF 0A40000-0A4FFFF 0A50000-0A5FFFF 0A60000-0A6FFFF 0A70000-0A7FFFF 0A80000-0A8FFFF 0A90000-0A9FFFF 0AA0000-0AAFFFF 0AB0000-0ABFFFF 0AC0000-0ACFFFF 0AD0000-0ADFFFF 0AE0000-0AEFFFF 0AF0000-0AFFFFF 0B00000-0B0FFFF 0B10000-0B1FFFF 0B20000-0B2FFFF 0B30000-0B3FFFF 0B40000-0B4FFFF 0B50000-0B5FFFF 0B60000-0B6FFFF 0B70000-0B7FFFF 0B80000-0B8FFFF 0B90000-0B9FFFF 0BA0000-0BAFFFF 0BB0000-0BBFFFF 0BC0000-0BCFFFF 0BD0000-0BDFFFF 0BE0000-0BEFFFF 32-bit Address Range (in hexadecimal) 478000-47FFFF 480000-487FFF 488000-48FFFF 490000-497FFF 498000-49FFFF 4A0000-4A7FFF 4A8000-4AFFFF 4B0000-4B7FFF 4B8000-4BFFFF 4C0000-4C7FFF 4C8000-4CFFFF 4D0000-4D7FFF 4D8000-4DFFFF 4E0000-4E7FFF 4E8000-4EFFFF 4F0000-4F7FFF 4F8000-4FFFFF 500000-507FFF 508000-50FFFF 510000-517FFF 518000-51FFFF 520000-527FFF 528000-52FFFF 530000-537FFF 538000-53FFFF 540000-547FFF 548000-54FFFF 550000-557FFF 558000-55FFFF 560000-567FFF 568000-56FFFF 570000-577FFF 578000-57FFFF 580000-587FFF 588000-58FFFF 590000-597FFF 598000-59FFFF 5A0000-5A7FFF 5A8000-5AFFFF 5B0000-5B7FFF 5B8000-5BFFFF 5C0000-5C7FFF 5C8000-5CFFFF 5D0000-5D7FFF 5D8000-5DFFFF 5E0000-5E7FFF 5E8000-5EFFFF 5F0000-5F7FFF
Sector SA143 SA144 SA145 SA146 SA147 SA148 SA149 SA150 SA151 SA152 SA153 SA154 SA155 SA156 SA157 SA158 SA159 SA160 SA161 SA162 SA163 SA164 SA165 SA166 SA167 SA168 SA169 SA170 SA171 SA172 SA173 SA174 SA175 SA176 SA177 SA178 SA179 SA180 SA181 SA182 SA183 SA184 SA185 SA186 SA187 SA188 SA189 SA190 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
A23-A15 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
October 9, 2003
Am29LV2562M
15
PRELIMINARY Table 2. Sector Address Table (Continued)
Sector Size (Kwords/Kdoublewords) 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 16-bit Address Range (in hexadecimal) 0BF0000-0BFFFFF 0C00000-0C0FFFF 0C10000-0C1FFFF 0C20000-0C2FFFF 0C30000-0C3FFFF 0C40000-0C4FFFF 0C50000-0C5FFFF 0C60000-0C6FFFF 0C70000-0C7FFFF 0C80000-0C8FFFF 0C90000-0C9FFFF 0CA0000-0CAFFFF 0CB0000-0CBFFFF 0CC0000-0CCFFFF 0CD0000-0CDFFFF 0CE0000-0CEFFFF 0CF0000-0CFFFFF 0D00000-0D0FFFF 0D10000-0D1FFFF 0D20000-0D2FFFF 0D30000-0D3FFFF 0D40000-0D4FFFF 0D50000-0D5FFFF 0D60000-0D6FFFF 0D70000-0D7FFFF 0D80000-0D8FFFF 0D90000-0D9FFFF 0DA0000-0DAFFFF 0DB0000-0DBFFFF 0DC0000-0DCFFFF 0DD0000-0DDFFFF 0DE0000-0DEFFFF 0DF0000-0DFFFFF 0E00000-0E0FFFF 0E10000-0E1FFFF 0E20000-0E2FFFF 0E30000-0E3FFFF 0E40000-0E4FFFF 0E50000-0E5FFFF 0E60000-0E6FFFF 0E70000-0E7FFFF 0E80000-0E8FFFF 0E90000-0E9FFFF 0EA0000-0EAFFFF 0EB0000-0EBFFFF 0EC0000-0ECFFFF 0ED0000-0EDFFFF 0EE0000-0EEFFFF 32-bit Address Range (in hexadecimal) 5F8000-5FFFFF 600000-607FFF 608000-60FFFF 610000-617FFF 618000-61FFFF 620000-627FFF 628000-62FFFF 630000-637FFF 638000-63FFFF 640000-647FFF 648000-64FFFF 650000-657FFF 658000-65FFFF 660000-667FFF 668000-66FFFF 670000-677FFF 678000-67FFFF 680000-687FFF 688000-68FFFF 690000-697FFF 698000-69FFFF 6A0000-6A7FFF 6A8000-6AFFFF 6B0000-6B7FFF 6B8000-6BFFFF 6C0000-6C7FFF 6C8000-6CFFFF 6D0000-6D7FFF 6D8000-6DFFFF 6E0000-6E7FFF 6E8000-6EFFFF 6F0000-6F7FFF 6F8000-6FFFFF 700000-707FFF 708000-70FFFF 710000-717FFF 718000-71FFFF 720000-727FFF 728000-72FFFF 730000-737FFF 738000-73FFFF 740000-747FFF 748000-74FFFF 750000-757FFF 758000-75FFFF 760000-767FFF 768000-76FFFF 770000-777FFF
Sector SA191 SA192 SA193 SA194 SA195 SA196 SA197 SA198 SA199 SA200 SA201 SA202 SA203 SA204 SA205 SA206 SA207 SA208 SA209 SA210 SA211 SA212 SA213 SA214 SA215 SA216 SA217 SA218 SA219 SA220 SA221 SA222 SA223 SA224 SA225 SA226 SA227 SA228 SA229 SA230 SA231 SA232 SA233 SA234 SA235 SA236 SA237 SA238 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
A23-A15 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16
Am29LV2562M
October 9, 2003
PRELIMINARY Table 2. Sector Address Table (Continued)
Sector Size (Kwords/Kdoublewords) 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 16-bit Address Range (in hexadecimal) 0EF0000-0EFFFFF 0F00000-0F0FFFF 0F10000-0F1FFFF 0F20000-0F2FFFF 0F30000-0F3FFFF 0F40000-0F4FFFF 0F50000-0F5FFFF 0F60000-0F6FFFF 0F70000-0F7FFFF 0F80000-0F8FFFF 0F90000-0F9FFFF 0FA0000-0FAFFFF 0FB0000-0FBFFFF 0FC0000-0FCFFFF 0FD0000-0FDFFFF 0FE0000-0FEFFFF 0FF0000-0FFFFFF 1000000-100FFFF 1010000-101FFFF 1020000-102FFFF 1030000-103FFFF 1040000-104FFFF 1050000-105FFFF 1060000-106FFFF 1070000-107FFFF 1080000-108FFFF 1090000-109FFFF 10A0000-10AFFFF 10B0000-10BFFFF 10C0000-10CFFFF 10D0000-10DFFFF 10E0000-10EFFFF 10F0000-10FFFFF 1100000-110FFFF 1110000-111FFFF 1120000-112FFFF 1130000-113FFFF 1140000-114FFFF 1150000-115FFFF 1160000-116FFFF 1170000-117FFFF 1180000-118FFFF 1190000-119FFFF 11A0000-11AFFFF 11B0000-11BFFFF 11C0000-11CFFFF 11D0000-11DFFFF 11E0000-11EFFFF 32-bit Address Range (in hexadecimal) 778000-77FFFF 780000-787FFF 788000-78FFFF 790000-797FFF 798000-79FFFF 7A0000-7A7FFF 7A8000-7AFFFF 7B0000-7B7FFF 7B8000-7BFFFF 7C0000-7C7FFF 7C8000-7CFFFF 7D0000-7D7FFF 7D8000-7DFFFF 7E0000-7E7FFF 7E8000-7EFFFF 7F0000-7F7FFF 7F8000-7FFFFF 800000-807FFF 808000-80FFFF 810000-817FFF 818000-81FFFF 820000-827FFF 828000-82FFFF 830000-837FFF 838000-83FFFF 840000-847FFF 848000-84FFFF 850000-857FFF 858000-85FFFF 860000-867FFF 868000-86FFFF 870000-877FFF 878000-87FFFF 880000-887FFF 888000-88FFFF 890000-897FFF 898000-89FFFF 8A0000-8A7FFF 8A8000-8AFFFF 8B0000-8B7FFF 8B8000-8BFFFF 8C0000-8C7FFF 8C8000-8CFFFF 8D0000-8D7FFF 8D8000-8DFFFF 8E0000-8E7FFF 8E8000-8EFFFF 8F0000-8F7FFF
Sector SA239 SA240 SA241 SA242 SA243 SA244 SA245 SA246 SA247 SA248 SA249 SA250 SA251 SA252 SA253 SA254 SA255 SA256 SA257 SA258 SA259 SA260 SA261 SA262 SA263 SA264 SA265 SA266 SA267 SA268 SA269 SA270 SA271 SA272 SA273 SA274 SA275 SA276 SA277 SA278 SA279 SA280 SA281 SA282 SA283 SA284 SA285 SA286 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
A23-A15 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
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PRELIMINARY Table 2. Sector Address Table (Continued)
Sector Size (Kwords/Kdoublewords) 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 16-bit Address Range (in hexadecimal) 11F0000-11FFFFF 1200000-120FFFF 1210000-121FFFF 1220000-122FFFF 1230000-123FFFF 1240000-124FFFF 1250000-125FFFF 1260000-126FFFF 1270000-127FFFF 1280000-128FFFF 1290000-129FFFF 12A0000-12AFFFF 12B0000-12BFFFF 12C0000-12CFFFF 12D0000-12DFFFF 12E0000-12EFFFF 12F0000-12FFFFF 1300000-130FFFF 1310000-131FFFF 1320000-132FFFF 1330000-133FFFF 1340000-134FFFF 1350000-135FFFF 1360000-136FFFF 1370000-137FFFF 1380000-138FFFF 1390000-139FFFF 13A0000-13AFFFF 13B0000-13BFFFF 13C0000-13CFFFF 13D0000-13DFFFF 13E0000-13EFFFF 13F0000-13FFFFF 1400000-140FFFF 1410000-141FFFF 1420000-142FFFF 1430000-143FFFF 1440000-144FFFF 1450000-145FFFF 1460000-146FFFF 1470000-147FFFF 1480000-148FFFF 1490000-149FFFF 14A0000-14AFFFF 14B0000-14BFFFF 14C0000-14CFFFF 14D0000-14DFFFF 14E0000-14EFFFF 32-bit Address Range (in hexadecimal) 8F8000-8FFFFF 900000-907FFF 908000-90FFFF 910000-917FFF 918000-91FFFF 920000-927FFF 928000-92FFFF 930000-937FFF 938000-93FFFF 940000-947FFF 948000-94FFFF 950000-957FFF 958000-95FFFF 960000-967FFF 968000-96FFFF 970000-977FFF 978000-97FFFF 980000-987FFF 988000-98FFFF 990000-997FFF 998000-99FFFF 9A0000-9A7FFF 9A8000-9AFFFF 9B0000-9B7FFF 9B8000-9BFFFF 9C0000-9C7FFF 9C8000-9CFFFF 9D0000-9D7FFF 9D8000-9DFFFF 9E0000-9E7FFF 9E8000-9EFFFF 9F0000-9F7FFF 9F8000-9FFFFF A00000-A07FFF A08000-A0FFFF A10000-A17FFF A18000-A1FFFF A20000-A27FFF A28000-A2FFFF A30000-A37FFF A38000-A3FFFF A40000-A47FFF A48000-A4FFFF A50000-A57FFF A58000-A5FFFF A60000-A67FFF A68000-A6FFFF A70000-A77FFF
Sector SA287 SA288 SA289 SA290 SA291 SA292 SA293 SA294 SA295 SA296 SA297 SA298 SA299 SA300 SA301 SA302 SA303 SA304 SA305 SA306 SA307 SA308 SA309 SA310 SA311 SA312 SA313 SA314 SA315 SA316 SA317 SA318 SA319 SA320 SA321 SA322 SA323 SA324 SA325 SA326 SA327 SA328 SA329 SA330 SA331 SA332 SA333 SA334 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
A23-A15 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
18
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PRELIMINARY Table 2. Sector Address Table (Continued)
Sector Size (Kwords/Kdoublewords) 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 16-bit Address Range (in hexadecimal) 14F0000-14FFFFF 1500000-150FFFF 1510000-151FFFF 1520000-152FFFF 1530000-153FFFF 1540000-154FFFF 1550000-155FFFF 1560000-156FFFF 1570000-157FFFF 1580000-158FFFF 1590000-159FFFF 15A0000-15AFFFF 15B0000-15BFFFF 15C0000-15CFFFF 15D0000-15DFFFF 15E0000-15EFFFF 15F0000-15FFFFF 1600000-160FFFF 1610000-161FFFF 1620000-162FFFF 1630000-163FFFF 1640000-164FFFF 1650000-165FFFF 1660000-166FFFF 1670000-167FFFF 1680000-168FFFF 1690000-169FFFF 16A0000-16AFFFF 16B0000-16BFFFF 16C0000-16CFFFF 16D0000-16DFFFF 16E0000-16EFFFF 16F0000-16FFFFF 1700000-170FFFF 1710000-171FFFF 1720000-172FFFF 1730000-173FFFF 1740000-174FFFF 1750000-175FFFF 1760000-176FFFF 1770000-177FFFF 1780000-178FFFF 1790000-179FFFF 17A0000-17AFFFF 17B0000-17BFFFF 17C0000-17CFFFF 17D0000-17DFFFF 17E0000-17EFFFF 32-bit Address Range (in hexadecimal) A78000-A7FFFF A80000-A87FFF A88000-A8FFFF A90000-A97FFF A98000-A9FFFF AA0000-AA7FFF AA8000-AAFFFF AB0000-AB7FFF AB8000-ABFFFF AC0000-AC7FFF AC8000-ACFFFF AD0000-AD7FFF AD8000-ADFFFF AE0000-AE7FFF AE8000-AEFFFF AF0000-AF7FFF AF8000-AFFFFF B00000-B07FFF B08000-B0FFFF B10000-B17FFF B18000-B1FFFF B20000-B27FFF B28000-B2FFFF B30000-B37FFF B38000-B3FFFF B40000-B47FFF B48000-B4FFFF B50000-B57FFF B58000-B5FFFF B60000-B67FFF B68000-B6FFFF B70000-B77FFF B78000-B7FFFF B80000-B87FFF B88000-B8FFFF B90000-B97FFF B98000-B9FFFF BA0000-BA7FFF BA8000-BAFFFF BB0000-BB7FFF BB8000-BBFFFF BC0000-BC7FFF BC8000-BCFFFF BD0000-BD7FFF BD8000-BDFFFF BE0000-BE7FFF BE8000-BEFFFF BF0000-BF7FFF
Sector SA335 SA336 SA337 SA338 SA339 SA340 SA341 SA342 SA343 SA344 SA345 SA346 SA347 SA348 SA349 SA350 SA351 SA352 SA353 SA354 SA355 SA356 SA357 SA358 SA359 SA360 SA361 SA362 SA363 SA364 SA365 SA366 SA367 SA368 SA369 SA370 SA371 SA372 SA373 SA374 SA375 SA376 SA377 SA378 SA379 SA380 SA381 SA382 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
A23-A15 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
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PRELIMINARY Table 2. Sector Address Table (Continued)
Sector Size (Kwords/Kdoublewords) 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 16-bit Address Range (in hexadecimal) 17F0000-17FFFFF 1800000-180FFFF 1810000-181FFFF 1820000-182FFFF 1830000-183FFFF 1840000-184FFFF 1850000-185FFFF 1860000-186FFFF 1870000-187FFFF 1880000-188FFFF 1890000-189FFFF 18A0000-18AFFFF 18B0000-18BFFFF 18C0000-18CFFFF 18D0000-18DFFFF 18E0000-18EFFFF 18F0000-18FFFFF 1900000-190FFFF 1910000-191FFFF 1920000-192FFFF 1930000-193FFFF 1940000-194FFFF 1950000-195FFFF 1960000-196FFFF 1970000-197FFFF 1980000-198FFFF 1990000-199FFFF 19A0000-19AFFFF 19B0000-19BFFFF 19C0000-19CFFFF 19D0000-19DFFFF 19E0000-19EFFFF 19F0000-19FFFFF 1A00000-1A0FFFF 1A10000-1A1FFFF 1A20000-1A2FFFF 1A30000-1A3FFFF 1A40000-1A4FFFF 1A50000-1A5FFFF 1A60000-1A6FFFF 1A70000-1A7FFFF 1A80000-1A8FFFF 1A90000-1A9FFFF 1AA0000-1AAFFFF 1AB0000-1ABFFFF 1AC0000-1ACFFFF 1AD0000-1ADFFFF 1AE0000-1AEFFFF 32-bit Address Range (in hexadecimal) BF8000-BFFFFF C00000-C07FFF C08000-C0FFFF C10000-C17FFF C18000-C1FFFF C20000-C27FFF C28000-C2FFFF C30000-C37FFF C38000-C3FFFF C40000-C47FFF C48000-C4FFFF C50000-C57FFF C58000-C5FFFF C60000-C67FFF C68000-C6FFFF C70000-C77FFF C78000-C7FFFF C80000-C87FFF C88000-C8FFFF C90000-C97FFF C98000-C9FFFF CA0000-CA7FFF CA8000-CAFFFF CB0000-CB7FFF CB8000-CBFFFF CC0000-CC7FFF CC8000-CCFFFF CD0000-CD7FFF CD8000-CDFFFF CE0000-CE7FFF CE8000-CEFFFF CF0000-CF7FFF CF8000-CFFFFF D00000-D07FFF D08000-D0FFFF D10000-D17FFF D18000-D1FFFF D20000-D27FFF D28000-D2FFFF D30000-D37FFF D38000-D3FFFF D40000-D47FFF D48000-D4FFFF D50000-D57FFF D58000-D5FFFF D60000-D67FFF D68000-D6FFFF D70000-D77FFF
Sector SA383 SA384 SA385 SA386 SA387 SA388 SA389 SA390 SA391 SA392 SA393 SA394 SA395 SA396 SA397 SA398 SA399 SA400 SA401 SA402 SA403 SA404 SA405 SA406 SA407 SA408 SA409 SA410 SA411 SA412 SA413 SA414 SA415 SA416 SA417 SA418 SA419 SA420 SA421 SA422 SA423 SA424 SA425 SA426 SA427 SA428 SA429 SA430 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
A23-A15 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
20
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PRELIMINARY Table 2. Sector Address Table (Continued)
Sector Size (Kwords/Kdoublewords) 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 16-bit Address Range (in hexadecimal) 1AF0000-1AFFFFF 1B00000-1B0FFFF 1B10000-1B1FFFF 1B20000-1B2FFFF 1B30000-1B3FFFF 1B40000-1B4FFFF 1B50000-1B5FFFF 1B60000-1B6FFFF 1B70000-1B7FFFF 1B80000-1B8FFFF 1B90000-1B9FFFF 1BA0000-1BAFFFF 1BB0000-1BBFFFF 1BC0000-1BCFFFF 1BD0000-1BDFFFF 1BE0000-1BEFFFF 1BF0000-1BFFFFF 1C00000-1C0FFFF 1C10000-1C1FFFF 1C20000-1C2FFFF 1C30000-1C3FFFF 1C40000-1C4FFFF 1C50000-1C5FFFF 1C60000-1C6FFFF 1C70000-1C7FFFF 1C80000-1C8FFFF 1C90000-1C9FFFF 1CA0000-1CAFFFF 1CB0000-1CBFFFF 1CC0000-1CCFFFF 1CD0000-1CDFFFF 1CE0000-1CEFFFF 1CF0000-1CFFFFF 1D00000-1D0FFFF 1D10000-1D1FFFF 1D20000-1D2FFFF 1D30000-1D3FFFF 1D40000-1D4FFFF 1D50000-1D5FFFF 1D60000-1D6FFFF 1D70000-1D7FFFF 1D80000-1D8FFFF 1D90000-1D9FFFF 1DA0000-1DAFFFF 1DB0000-1DBFFFF 1DC0000-1DCFFFF 1DD0000-1DDFFFF 1DE0000-1DEFFFF 32-bit Address Range (in hexadecimal) D78000-D7FFFF D80000-D87FFF D88000-D8FFFF D90000-D97FFF D98000-D9FFFF DA0000-DA7FFF DA8000-DAFFFF DB0000-DB7FFF DB8000-DBFFFF DC0000-DC7FFF DC8000-DCFFFF DD0000-DD7FFF DD8000-DDFFFF DE0000-DE7FFF DE8000-DEFFFF DF0000-DF7FFF DF8000-DFFFFF E00000-E07FFF E08000-E0FFFF E10000-E17FFF E18000-E1FFFF E20000-E27FFF E28000-E2FFFF E30000-E37FFF E38000-E3FFFF E40000-E47FFF E48000-E4FFFF E50000-E57FFF E58000-E5FFFF E60000-E67FFF E68000-E6FFFF E70000-E77FFF E78000-E7FFFF E80000-E87FFF E88000-E8FFFF E90000-E97FFF E98000-E9FFFF EA0000-EA7FFF EA8000-EAFFFF EB0000-EB7FFF EB8000-EBFFFF EC0000-EC7FFF EC8000-ECFFFF ED0000-ED7FFF ED8000-EDFFFF EE0000-EE7FFF EE8000-EEFFFF EF0000-EF7FFF
Sector SA431 SA432 SA433 SA434 SA435 SA436 SA437 SA438 SA439 SA440 SA441 SA442 SA443 SA444 SA445 SA446 SA447 SA448 SA449 SA450 SA451 SA452 SA453 SA454 SA455 SA456 SA457 SA458 SA459 SA460 SA461 SA462 SA463 SA464 SA465 SA466 SA467 SA468 SA469 SA470 SA471 SA472 SA473 SA474 SA475 SA476 SA477 SA478 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
A23-A15 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
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PRELIMINARY Table 2. Sector Address Table (Continued)
Sector Size (Kwords/Kdoublewords) 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 16-bit Address Range (in hexadecimal) 1DF0000-1DFFFFF 1E00000-1E0FFFF 1E10000-1E1FFFF 1E20000-1E2FFFF 1E30000-1E3FFFF 1E40000-1E4FFFF 1E50000-1E5FFFF 1E60000-1E6FFFF 1E70000-1E7FFFF 1E80000-1E8FFFF 1E90000-1E9FFFF 1EA0000-1EAFFFF 1EB0000-1EBFFFF 1EC0000-1ECFFFF 1ED0000-1EDFFFF 1EE0000-1EEFFFF 1EF0000-1EFFFFF 1F00000-1F0FFFF 1F10000-1F1FFFF 1F20000-1F2FFFF 1F30000-1F3FFFF 1F40000-1F4FFFF 1F50000-1F5FFFF 1F60000-1F6FFFF 1F70000-1F7FFFF 1F80000-1F8FFFF 1F90000-1F9FFFF 1FA0000-1FAFFFF 1FB0000-1FBFFFF 1FC0000-1FCFFFF 1FD0000-1FDFFFF 1FE0000-1FEFFFF 1FF0000-1FFFFFF 32-bit Address Range (in hexadecimal) EF8000-EFFFFF F00000-F07FFF F08000-F0FFFF F10000-F17FFF F18000-F1FFFF F20000-F27FFF F28000-F2FFFF F30000-F37FFF F38000-F3FFFF F40000-F47FFF F48000-F4FFFF F50000-F57FFF F58000-F5FFFF F60000-F67FFF F68000-F6FFFF F70000-F77FFF F78000-F7FFFF F80000-F87FFF F88000-F8FFFF F90000-F97FFF F98000-F9FFFF FA0000-FA7FFF FA8000-FAFFFF FB0000-FB7FFF FB8000-FBFFFF FC0000-FC7FFF FC8000-FCFFFF FD0000-FD7FFF FD8000-FDFFFF FE0000-FE7FFF FE8000-FEFFFF FF0000-FF7FFF FF8000-FFFFFF
Sector SA479 SA480 SA481 SA482 SA483 SA484 SA485 SA486 SA487 SA488 SA489 SA490 SA491 SA492 SA493 SA494 SA495 SA496 SA497 SA498 SA499 SA500 SA501 SA502 SA503 SA504 SA505 SA506 SA507 SA508 SA509 SA510 SA511 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
A23-A15 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
22
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PRELIMINARY
Autoselect Mode
The autoselect mode provides manufacturer and device identification, and sector group protection verification, through identifier codes output on DQ7-DQ0. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. However, the autoselect codes can also be accessed in-system through the command register. When using programming equipment, the autoselect mode requires VID on address pin A9. Address pins A6, A3, A2, A1, and A0 must be as shown in Table 3.
In addition, when verifying sector protection, the sector address must appear on the appropriate highest order address bits (see Table 2). Table 3 shows the remaining address bits that are don't care. When all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on DQ7-DQ0. To access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in Tables 10 and 11. This method does not require VID. Refer to the Autoselect Command Sequence section for more information.
Table 3.
Description CE# OE# WE#
Autoselect Codes, (High Voltage Method)
A9 A8 to A7 X A6 A5 to A4 X A3 to A2 L L
A23 A14 to to A15 A10 X X
DQ23 to DQ16
A1 A0
WORD# WORD# = VIH = VIL
00 22 22 22 X X X X X X
DQ7 to DQ0
Manufacturer ID: AMD Device ID Cycle 1 Cycle 2 Cycle 3
L
L
H
VID
L
L L H H H
L H L H L
01h 7Eh 12h 01h 01h (protected), 00h (unprotected) 98h (factory locked), 18h (not factory locked)
L
L
H
X
X
VID
X
L
X
H H
Sector Group Protection Verification SecSi Sector Indicator Bit (DQ7), WP# protects highest address sector SecSi Sector Indicator Bit (DQ7), WP# protects lowest address sector
L
L
H
SA
X
VID
X
L
X
L
L
L
H
X
X
VID
X
L
X
L
H
H
X
X
L
L
H
X
X
VID
X
L
X
L
H
H
X
X
88h (factory locked), 08h (not factory locked)
Legend: L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don't care.
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PRELIMINARY
Sector Group Protection and Unprotection
The hardware sector group protection feature disables both program and erase operations in any sector group. The hardware sector group unprotection feature re-enables both program and erase operations in previously protected sector groups. Sector group protection/unprotection can be implemented via two methods. Sector group protection/unprotection requires VID on the RESET# pin only, and can be implemented either in-system or via programming equipment. Figure 2 shows the algorithms and Figure 23 shows the timing diagram. For sector group unprotect, all unprotected sector groups must first be protected prior to the first sector group unprotect write cycle. Note that the sector group unprotect algorithm unprotects all sector groups in parallel. All previously protected sector groups must be individually re-protected. The device is shipped with all sector groups unprotected. AMD offers the option of programming and protecting sector groups at its factory prior to shipping the device through AMD's ExpressFlashTM Service. Contact an AMD representative for details. It is possible to determine whether a sector group is protected or unprotected. See the Autoselect Mode section for details. Table 4. Sector Group Protection/Unprotection Address Table
A23-A15 000000000 000000001 000000010 000000011 0000001xx 0000010xx 0000011xx 0000100xx 0000101xx 0000110xx 0000111xx 0001000xx 0001001xx 0001010xx 0001011xx 0001100xx 0001101xx 0001110xx 0001111xx 0010000xx SA0 SA1 SA2 SA3 SA4-SA7 SA8-SA11 SA12-SA15 SA16-SA19 SA20-SA23 SA24-SA27 SA28-SA31 SA32-SA35 SA36-SA39 SA40-SA43 SA44-SA47 SA48-SA51 SA52-SA55 SA56-SA59 SA60-SA63 SA64-SA67
Sector Group SA68-SA71 SA72-SA75 SA76-SA79 SA80-SA83 SA84-SA87 SA88-SA91 SA92-SA95 SA96-SA99 SA100-SA103 SA104-SA107 SA108-SA111 SA112-SA115 SA116-SA119 SA120-SA123 SA124-SA127 SA128-SA131 SA132-SA135 SA136-SA139 SA140-SA143 SA144-SA147 SA148-SA151 SA152-SA155 SA156-SA159 SA160-SA163 SA164-SA167 SA168-SA171 SA172-SA175 SA176-SA179 SA180-SA183 SA184-SA187 SA188-SA191 SA192-SA195 SA196-SA199 SA200-SA203 SA204-SA207 SA208-SA211 SA212-SA215 SA216-SA219 SA220-SA223 SA224-SA227 SA228-SA231 SA232-SA235 SA236-SA239 SA240-SA243 SA244-SA247
A23-A15 0010001xx 0010010xx 0010011xx 0010100xx 0010101xx 0010110xx 0010111xx 0011000xx 0011001xx 0011010xx 0011011xx 0011100xx 0011101xx 0011110xx 0011111xx 0100000xx 0100001xx 0100010xx 0100011xx 0100100xx 0100101xx 0100110xx 0100111xx 0101000xx 0101001xx 0101010xx 0101011xx 0101100xx 0101101xx 0101110xx 0101111xx 0110000xx 0110001xx 0110010xx 0110011xx 0110100xx 0110101xx 0110110xx 0110111xx 0111000xx 0111001xx 0111010xx 0111011xx 0111100xx 0111101xx
Sector Group
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PRELIMINARY
Sector Group SA248-SA251 SA252-SA255 SA256-SA259 SA260-SA263 SA264-SA267 SA268-SA271 SA272-SA275 SA276-SA279 SA280-SA283 SA284-SA287 SA288-SA291 SA292-SA295 SA296-SA299 SA300-SA303 SA304-SA307 SA308-SA311 SA312-SA315 SA316-SA319 SA320-SA323 SA324-SA327 SA328-SA331 SA332-SA335 SA336-SA339 SA340-SA343 SA344-SA347 SA348-SA351 SA352-SA355 SA356-SA359 SA360-SA363 SA364-SA367 SA368-SA371 SA372-SA375 SA376-SA379 SA380-SA383 SA384-SA387 SA388-SA391 SA392-SA395 SA396-SA399 SA400-SA403 SA404-SA407 SA408-SA411 SA412-SA415 SA416-SA419 SA420-SA423 SA424-SA427 A23-A15 0111110xx 0111111xx 1000000xx 1000001xx 1000010xx 1000011xx 1000100xx 1000101xx 1000110xx 1000111xx 1001000xx 1001001xx 1001010xx 1001011xx 1001100xx 1001101xx 1001110xx 1001111xx 1010000xx 1010001xx 1010010xx 1010011xx 1010100xx 1010101xx 1010110xx 1010111xx 1011000xx 1011001xx 1011010xx 1011011xx 1011100xx 1011101xx 1011110xx 1011111xx 1100000xx 1100001xx 1100010xx 1100011xx 1100100xx 1100101xx 1100110xx 1100111xx 1101000xx 1101001xx 1101010xx Sector Group SA428-SA431 SA432-SA435 SA436-SA439 SA440-SA443 SA444-SA447 SA448-SA451 SA452-SA455 SA456-SA459 SA460-SA463 SA464-SA467 SA468-SA471 SA472-SA475 SA476-SA479 SA480-SA483 SA484-SA487 SA488-SA491 SA492-SA495 SA496-SA499 SA500-SA503 SA504-SA507 SA508 SA509 SA510 SA511 A23-A15 1101011xx 1101100xx 1101101xx 1101110xx 1101111xx 1110000xx 1110001xx 1110010xx 1110011xx 1110100xx 1110101xx 1110110xx 1110111xx 1111000xx 1111001xx 1111010xx 1111011xx 1111100xx 1111101xx 1111110xx 111111100 111111101 111111110 111111111
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PRELIMINARY
Write Protect (WP#)
The Write Protect function provides a hardware method of protecting the first or last sector without using VID. Write Protect is one of two functions provided by the WP#/ACC input. If the system asserts VIL on the WP#/ACC pin, the device disables program and erase functions in the first or last sector independently of whether those sectors were protected or unprotected using the method described in "Sector Group Protection and Unprotection". Note that if WP#/ACC is at VIL when the device is in the standby mode, the maximum input load current is increased. See the table in "DC Characteristics". If the system asserts VIH on the WP#/ACC pin, the device reverts to whether the first or last sector was previously set to be protected or unprotected using the method described in "Sector Group Protection and Unprotection". Note that WP# has an internal pullup; when unconnected, WP# is at VIH.
START
RESET# = VID (Note 1) Perform Erase or Program Operations
RESET# = VIH
Temporary Sector Unprotect Completed (Note 2)
Temporary Sector Group Unprotect
This feature allows temporary unprotection of previously protected sector groups to change data in-system. The Sector Group Unprotect mode is activated by setting the RESET# pin to VID. During this mode, formerly protected sector groups can be programmed or erased by selecting the sector group addresses. Once VID is removed from the RESET# pin, all the previously protected sector groups are protected again. Figure 1 shows the algorithm, and Figure 22 shows the timing diagrams, for this feature.
Notes: 1. All protected sector groups unprotected (If WP# = VIL, the first or last sector will remain protected). 2. All previously protected sector groups are protected once again.
Figure 1. Temporary Sector Group Unprotect Operation
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PRELIMINARY
START PLSCNT = 1 RESET# = VID Wait 1 s Protect all sector groups: The indicated portion of the sector group protect algorithm must be performed for all unprotected sector groups prior to issuing the first sector group unprotect address
START PLSCNT = 1 RESET# = VID Wait 1 s
Temporary Sector Group Unprotect Mode
No
First Write Cycle = 60h?
First Write Cycle = 60h?
No
Temporary Sector Group Unprotect Mode
Yes Set up sector group address No
Yes All sector groups protected? Yes Set up first sector group address Sector Group Unprotect: Write 60h to sector group address with A6 = 1, A1 = 1, A0 = 0 Reset PLSCNT = 1 Wait 15 ms
Sector Group Protect: Write 60h to sector group address with A6 = 0, A1 = 1, A0 = 0
Wait 150 s
Increment PLSCNT
Verify Sector Group Protect: Write 40h to sector group address twith A6 = 0, A1 = 1, A0 = 0
Read from sector group address with A6 = 0, A1 = 1, A0 = 0 No No PLSCNT = 25? Data = 01h?
Increment PLSCNT
Verify Sector Group Unprotect: Write 40h to sector group address with A6 = 1, A1 = 1, A0 = 0
Yes Yes Protect another sector group? No Remove VID from RESET# Yes
Read from sector group address with A6 = 1, A1 = 1, A0 = 0 No Set up next sector group address Data = 00h?
No
PLSCNT = 1000? Yes
Device failed
Yes
Device failed Write reset command
Last sector group verified? Yes Remove VID from RESET#
No
Sector Group Protect Algorithm
Sector Group Protect complete
Sector Group Unprotect Algorithm
Write reset command
Sector Group Unprotect complete
Figure 2.
In-System Sector Group Protect/Unprotect Algorithms
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PRELIMINARY
SecSi (Secured Silicon) Sector Flash Memory Region
The SecSi (Secured Silicon) Sector feature provides a Flash memory region that enables permanent part identification through an Electronic Serial Number (ESN). The SecSi Sector is 128 doublewords/256 words in length, and uses SecSi Sector Indicator Bits (DQ7 and DQ15) to indicate whether or not the SecSi Sector is locked when shipped from the factory. These bits are permanently set at the factory and cannot be changed, which prevents cloning of a factory locked part. This ensures the security of the ESN once the product is shipped to the field. AMD offers the device with the SecSi Sector either fac t or y l ocke d or c u s t om e r l o ckabl e. T he fac tory-locked version is always protected when shipped from the factory, and has the SecSi (Secured Silicon) Sector Indicator Bits permanently set to a "1." The customer-lockable version is shipped with the SecSi Sector unprotected, allowing customers to program the sector after receiving the device. The customer-lockable version also has the SecSi Sector Indicator Bit permanently set to a "0." Thus, the SecSi Sector Indicator Bits prevent customer-lockable devices from being used to replace devices that are factory locked. The SecSi sector address space in this device is allocated as follows: Table 5.
SecSi Sector Address Range x32 000000h- 000007h 000008h- 00007Fh x16 000000h- 00000Fh 000010h- 0000FFh
Factory Locked: SecSi Sector Programmed and Protected At the Factory In devices with an ESN, the SecSi Sector is protected when the device is shipped from the factory. The SecSi Sector cannot be modified in any way. A factory locked device has an 8-doubleword/16-word random ESN at addresses 000000h-000007h. Customers may opt to have their code programmed by AMD through the AMD ExpressFlash service. The devices are then shipped from AMD's factory with the SecSi Sector permanently locked. Contact an AMD representative for details on using AMD's ExpressFlash service. Customer Lockable: SecSi Sector NOT Programmed or Protected At the Factory As an alternative to the factory-locked version, the device may be ordered such that the customer may program and protect the 128-doubleword/256 word SecSi sector. The system may program the SecSi Sector using the write-buffer, accelerated and/or unlock bypass methods, in addition to the standard programming command sequence. See To reduce power consumption read Lower Byte only.. Programming and protecting the SecSi Sector must be used with caution since, once protected, there is no procedure available for unprotecting the SecSi Sector area and none of the bits in the SecSi Sector memory space can be modified in any way. The SecSi Sector area can be protected using one of the following procedures: Write the three-cycle Enter SecSi Sector Region command sequence, and then follow the in-system sector protect algorithm as shown in Figure 2, except that RESET# may be at either VIH or VID. This allows in-system protection of the SecSi Sector without raising any device pin to a high voltage. Note that this method is only applicable to the SecSi Sector. To verify the protect/unprotect status of the SecSi Sector, follow the algorithm shown in Figure 3. Once the SecSi Sector is programmed, locked and verified, the system must write the Exit SecSi Sector Region command sequence to return to reading and writing within the remainder of the array.
SecSi Sector Contents
Standard Factory Locked ESN Unavailable ExpressFlash Factory Locked ESN or determined by customer Determined by customer Customer Lockable
Determined by customer
The system accesses the SecSi Sector through a command sequence (see "Enter SecSi Sector/Exit SecSi Sector Command Sequence"). After the system has written the Enter SecSi Sector command sequence, it may read the SecSi Sector by using the addresses normally occupied by the first sector (SA0). This mode of operation continues until the system issues the Exit SecSi Sector command sequence, or until power is removed from the device. On power-up, or following a hardware reset, the device reverts to sending commands to sector SA0.
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PRELIMINARY caused by spurious system level signals during VCC power-up and power-down transitions, or from system noise.
If data = 00h, SecSi Sector is unprotected. If data = 01h, SecSi Sector is protected.
START RESET# = VIH or VID Wait 1 ms Write 60h to any address
Low VCC Write Inhibit When VCC is less than VLKO, the device does not accept any write cycles. This protects data during VCC power-up and power-down. The command register and all internal program/erase circuits are disabled, and the device resets to the read mode. Subsequent writes are ignored until VCC is greater than VLKO. The system must provide the proper signals to the control pins to prevent unintentional writes when V CC is greater than VLKO. Write Pulse "Glitch" Protection
Remove VIH or VID from RESET#
Write 40h to SecSi Sector address with A6 = 0, A1 = 1, A0 = 0 Read from SecSi Sector address with A6 = 0, A1 = 1, A0 = 0
Write reset command
SecSi Sector Protect Verify complete
Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle. Logical Inhibit Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH or WE# = VIH. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a logical one. Power-Up Write Inhibit If WE# = CE# = VIL and OE# = V IH during power up, the device does not accept commands on the rising edge of WE#. The internal state machine is automatically reset to the read mode on power-up.
Figure 3.
SecSi Sector Protect Verify
Hardware Data Protection
The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to Tables 10 and 11 for command definitions). In addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be
COMMON FLASH MEMORY INTERFACE (CFI)
The Common Flash Interface (CFI) specification outlines device and host system software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. Software support can then be device-independent, JEDEC ID-independent, and forward- and backward-compatible for the specified flash device families. Flash vendors can standardize their existing interfaces for long-term compatibility. This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address 55h, any time the device is ready to read array data. The system can read CFI information at the addresses given in Tables 6-9. To terminate reading CFI data, the system must write the reset command. The system can also write the CFI query command when the device is in the autoselect mode. The device enters the CFI query mode, and the system can read CFI data at the addresses given in Tables 6-9. The system must write the reset command to return the device to reading array data. For further information, please refer to the CFI Specification and CFI Publication 100, available via the World Wide Web at http://www.amd.com/flash/cfi. Alternatively, contact an AMD representative for copies of these documents.
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PRELIMINARY Table 6.
Addresses (x32) 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah Data 00005151h 00005252h 00005959h 00000202h 00000000h 00004040h 00000000h 00000000h 00000000h 00000000h 00000000h Query Unique ASCII string "QRY"
CFI Query Identification String
Description
Primary OEM Command Set Address for Primary Extended Table Alternate OEM Command Set (00h = none exists) Address for Alternate OEM Extended Table (00h = none exists)
Table 7.
Addresses (x16) 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h Data 00002727h 00003636h 00000000h 00000000h 00000707h 00000707h 00000A0Ah 00000000h 00000101h 00000505h 00000404h 00000000h
System Interface String
Description
VCC Min. (write/erase) D7-D4: volt, D3-D0: 100 millivolt VCC Max. (write/erase) D7-D4: volt, D3-D0: 100 millivolt VPP Min. voltage (00h = no VPP pin present) VPP Max. voltage (00h = no VPP pin present) Typical timeout per single byte/word write 2N s Typical timeout for Min. size buffer write 2N s (00h = not supported) Typical timeout per individual block erase 2N ms Typical timeout for full chip erase 2N ms (00h = not supported) Max. timeout for byte/word write 2N times typical Max. timeout for buffer write 2N times typical Max. timeout per individual block erase 2N times typical Max. timeout for full chip erase 2N times typical (00h = not supported)
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PRELIMINARY Table 8.
Addresses (x16) 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch Data 00001919h 00000202h 00000000h 00000505h 00000000h 00000101h 0101FFFFh 00000101h 00000000h 00000101h 00000000h 00000000h 00000000h 00000000h 00000000h 00000000h 00000000h 00000000h 00000000h 00000000h 00000000h 00000000h Device Size = 2N byte Flash Device Interface description (refer to CFI publication 100) Max. number of byte in multi-byte write = 2N (00h = not supported) Number of Erase Block Regions within device (01h = uniform device, 02h = boot device) Erase Block Region 1 Information (refer to the CFI specification or CFI publication 100)
Device Geometry Definition
Description
Erase Block Region 2 Information (refer to CFI publication 100)
Erase Block Region 3 Information (refer to CFI publication 100)
Erase Block Region 4 Information (refer to CFI publication 100)
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PRELIMINARY Table 9.
Addresses (x16) 40h 41h 42h 43h 44h Data 00005050h 00005252h 00004949h 00003131h 00003333h Query-unique ASCII string "PRI" Major version number, ASCII Minor version number, ASCII Address Sensitive Unlock (Bits 1-0) 0 = Required, 1 = Not Required Process Technology (Bits 7-2) 0010b = 0.23 m MirrorBit 46h 47h 48h 49h 4Ah 4Bh 4Ch 4Dh 000000202h 00000101h 00000101h 00000404h 00000000h 00000000h 00000101h 0000B5B5h Erase Suspend 0 = Not Supported, 1 = To Read Only, 2 = To Read & Write Sector Protect 0 = Not Supported, X = Number of sectors in per group Sector Temporary Unprotect 00 = Not Supported, 01 = Supported Sector Protect/Unprotect scheme 04 = 29LV800 mode Simultaneous Operation 00 = Not Supported, X = Number of Sectors in Bank Burst Mode Type 00 = Not Supported, 01 = Supported Page Mode Type 00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page ACC (Acceleration) Supply Minimum 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV ACC (Acceleration) Supply Maximum 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV Top/Bottom Boot Sector Flag 4Fh 00000404h/ 00000505h 00h = Uniform Device without WP# protect, 02h = Bottom Boot Device, 03h = Top Boot Device, 04h = Uniform sectors bottom WP# protect, 05h = Uniform sectors top WP# protect Program Suspend 00h = Not Supported, 01h = Supported
Primary Vendor-Specific Extended Query
Description
45h
000000808h
4Eh
0000C5C5h
50h
00000101h
Note:To reduce power consumption read Lower Byte only.
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PRELIMINARY
COMMAND DEFINITIONS
Writing specific address and data commands or sequences into the command register initiates device operations. Tables 10 and 11 define the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. A reset command is then required to return the device to reading array data. All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on the rising edge of WE# or CE#, whichever happens first. Refer to the AC Characteristics section for timing diagrams.
the read mode. If the program command sequence is written while the device is in the Erase Suspend mode, writing the reset command returns the device to the erase-suspend-read mode. Once programming begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to the read mode. If the device entered the autoselect mode while in the Erase Suspend mode, writing the reset command returns the device to the erase-suspend-read mode. If DQ5 or DQ13 goes high during a program or erase operation, writing the reset command returns the device to the read mode (or erase-suspend-read mode if the device was in Erase Suspend). Note that if DQ1 or DQ9 goes high during a Write Buffer Programming operation, the system must write the Write-to-Buffer-Abort Reset command sequence to reset the device for the next operation.
Reading Array Data
The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. The device is ready to read array data after completing an Embedded Program or Embedded Erase algorithm. After the device accepts an Erase Suspend command, the device enters the erase-suspend-read mode, after which the system can read data from any non-erase-suspended sector. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See the Erase Suspend/Erase Resume Commands section for more information. The system must issue the reset command to return the device to the read (or erase-suspend-read) mode if DQ5 or DQ13 goes high during an active program or erase operation, or if the device is in the autoselect mode. See the next section, Reset Command, for more information. See also Requirements for Reading Array Data in the Device Bus Operations section for more information. The Read-Only Operations table provides the read parameters, and Figure 13 shows the timing diagram.
Autoselect Command Sequence
The autoselect command sequence allows the host system to access the manufacturer and device codes, and determine whether or not a sector is protected. Table 11 shows the address and data requirements. This method is an alternative to that shown in Table 3, which is intended for PROM programmers and requires V ID on address pin A9. The autoselect command sequence may be written to an address that is either in the read or erase-suspend-read mode. The autoselect command may not be written while the device is actively programming or erasing. The autoselect command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle that contains the autoselect command. The device then enters the autoselect mode. The system may read at any address any number of times without initiating another autoselect command sequence: A read cycle at address XX00h returns the manufacturer code. Three read cycles at addresses 01h, 0Eh, and 0Fh return the device code. A read cycle to an address containing a sector address (SA), and the address 02h on A7-A0 in doubleword mode retur ns 0101h if the sector is protected, or 0000h if it is unprotected. The system must write the reset command to return to the read mode (or erase-suspend-read mode if the device was previously in Erase Suspend).
Reset Command
Writing the reset command resets the device to the read or erase-suspend-read mode. Address bits are don't cares for this command. The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the device to the read mode. Once erasure begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the device to
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PRELIMINARY
Enter SecSi Sector/Exit SecSi Sector Command Sequence
The SecSi Sector region provides a secured data area containing an 8-doubleword/16-word random Electronic Serial Number (ESN). The system can access the SecSi Sector region by issuing the three-cycle Enter SecSi Sector command sequence. The device continues to access the SecSi Sector region until the system issues the four-cycle Exit SecSi Sector command sequence. The Exit SecSi Sector command sequence returns the device to normal operation. Tables 10 and 11 show the address and data requirements for both command sequences. See also "SecSi (Secured Silicon) Sector Flash Memory Region" for further information. Note that the ACC function and unlock bypass modes are not available when the SecSi Sector is enabled.
Unlock Bypass Command Sequence The unlock bypass feature allows the system to program words to the device faster than using the standard program command sequence. The unlock bypass command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the unlock bypass command, 2020h. The device then enters the unlock bypass mode. A two-cycle unlock bypass program command sequence is all that is required to program in this mode. The first cycle in this sequence contains the unlock bypass program command, A0A0h; the second cycle contains the program address and data. Additional data is programmed in the same manner. This mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total programming time. Tables 10 and 11 show the requirements for the command sequence. During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. The first cycle must contain the data 9090h. The second cycle must contain the data 00h. The device then returns to the read mode. Write Buffer Programming Write Buffer Programming allows the system write to a maximum of 16 doublewords/32 words in one programming operation. This results in faster effective programming time than the standard programming algorithms. The Write Buffer Programming command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the Write Buffer Load command written at the Sector Address in which programming will occur. The fourth cycle writes the sector address and the number of word locations, minus one, to be programmed. For example, if the system will program 6 unique address locations, then 0505h should be written to the device. This tells the device how many write buffer addresses will be loaded with data and therefore when to expect the Program Buffer to Flash command. The number of locations to program cannot exceed the size of the write buffer or the operation will abort. The fifth cycle writes the first address location and data to be programmed. The write-buffer-page is selected by address bits A23-A4. All subsequent add r e s s / d a t a p a i r s m u s t fa l l w i t h i n t h e selected-write-buffer-page. The system then writes the remaining address/data pairs into the write buffer. Write buffer locations may be loaded in any order. The write-buffer-page address must be the same for all address/data pairs loaded into the write buffer. (This means Write Buffer Programming cannot be performed across multiple write-buffer pages. This also
Doubleword/Word Program Command Sequence
Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further controls or timings. The device automatically provides internally generated program pulses and verifies the programmed cell margin. Tables 10 and 11 show the address and data requirements for the word program command sequence. When the Embedded Program algorithm is complete, the device then returns to the read mode and addresses are no longer latched. The system can determine the status of the program operation by using DQ7 and DQ15 or DQ6 and DQ14. Refer to the Write Operation Status section for information on these status bits. Any commands written to the device during the Embedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the program operation. The program command sequence should be reinitiated once the device has returned to the read mode, to ensure data integrity. Note that the SecSi Sector, autoselect, and CFI functions are unavailable when a program operation is in progress Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from "0" back to a "1." Attempting to do so may cause the device to set DQ5 and/or DQ13 = 1, or cause the DQ7 and/or DQ15, and DQ6 and/or DQ14 status bits to indicate the operation was successful. However, a succeeding read will show that the data is still "0." Only erase operations can convert a "0" to a "1."
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PRELIMINARY means that Write Buffer Programming cannot be performed across multiple sectors. If the system attempts to load programming data outside of the selected write-buffer page, the operation will abort. Note that if a Write Buffer address location is loaded multiple times, the address/data pair counter will be decremented for every data load operation. The host s y s t e m m u s t t h e r e fo r e a c c o u n t fo r l o a d i n g a write-buffer location more than once. The counter decrements for each data load operation, not for each unique write-buffer-address location. Note also that if an address location is loaded more than once into the buffer, the final data loaded for that address will be programmed. Once the specified number of write buffer locations have been loaded, the system must then write the Program Buffer to Flash command at the sector address. Any other address and data combination aborts the Write Buffer Programming operation. The device then begins programming. Data polling should be used while monitoring the last address location loaded into the write buffer. DQ7 and DQ15, DQ6 and DQ14, DQ5 and DQ13, and DQ1 and DQ9 should be monitored to determine the device status during Write Buffer Programming. The write-buffer programming operation can be suspended using the standard program suspend/resume commands. Upon successful completion of the Write Buffer Programming operation, the device is ready to execute the next command. The Write Buffer Programming Sequence can be aborted in the following ways: Load a value that is greater than the page buffer size during the Number of Locations to Program step. Write to an address in a sector different than the one specified during the Write-Buffer-Load command. Write an Address/Data pair to a different write-buffer-page than the one selected by the Starting Address during the write buffer data loading stage of the operation. Write data other than the Confirm Command after the specified number of data load cycles. The abort condition is indicated by DQ1 and DQ9 = 1, DQ7 and DQ15 = DATA# (for the last address location loaded), DQ6 and DQ14 = toggle, and DQ5 and DQ13 =0. A Write-to-Buffer-Abort Reset command sequence must be written to reset the device for the next operation. Note that the full 3-cycle Write-to-Buffer-Abort Reset command sequence is required when using Write-Buffer-Programming features in Unlock Bypass mode. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from "0" back to a "1." Attempting to do so may cause the device to set DQ5 and/or DQ13= 1, or cause the DQ7 and/or DQ15 and DQ6 and/or DQ14 status bits to indicate the operation was successful. However, a succeeding read will show that the data is still "0." Only erase operations can convert a "0" to a "1." Accelerated Program The device offers accelerated program operations through the WP#/ACC pin. When the system asserts VHH on the WP#/ACC pin, the device automatically enters the Unlock Bypass mode. The system may then write the two-cycle Unlock Bypass program command sequence. The device uses the higher voltage on the WP#/ACC pin to accelerate the operation. Note that the WP#/ACC pin must not be at V HH for operations other than accelerated programming, or device damage may result. WP# has an internal pullup; when unconnected, WP# is at VIH. Figure 5 illustrates the algorithm for the program operation. Refer to the Erase and Program Operations table in the AC Characteristics section for parameters, and Figure 16 for timing diagrams.
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PRELIMINARY
Write "Write to Buffer" command and Sector Address
Write number of addresses to program minus 1(WC) and Sector Address
Part of "Write to Buffer" Command Sequence
Write first address/data
Yes
WC = 0 ? No Abort Write to Buffer Operation? No Yes Write to buffer ABORTED. Must write "Write-to-buffer Abort Reset" command sequence to return to read mode. Write to a different sector address
(Note 1)
Write next address/data pair
WC = WC - 1
Write program buffer to flash sector address
Notes:
1. When Sector Address is specified, any address in the selected sector is acceptable. However, when loading Write-Buffer address locations with data, all addresses must fall within the selected Write-Buffer Page.
Read DQ7 - DQ0 at Last Loaded Address
2.
DQ7 and DQ15 may change simultaneously with DQ5 and DQ13. Therefore, DQ7 and DQ15 should be verified. If this flowchart location was reached because DQ5 and DQ13 = "1", then the device FAILED. If this flowchart location was reached because DQ1= "1", then the Write to Buffer operation was ABORTED. In either case, the proper reset command must be written before the device can begin another operation. If DQ1 and DQ9 =1, write the Write-Buffer-Programming-Abort-Reset command. if DQ5 and DQ13 =1, write the Reset command.
See Tables 10 and 11 for command sequences required for write buffer programming.
3.
DQ7 = Data? No No DQ1 = 1? Yes DQ5 = 1? Yes Read DQ7 - DQ0 with address = Last Loaded Address No
Yes
4.
(Note 2)
DQ7 = Data? No
Yes
(Note 3)
FAIL or ABORT
PASS
Figure 4.
Write Buffer Programming Operation
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Am29LV2562M
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PRELIMINARY
Program Suspend/Program Resume Command Sequence
START
Write Program Command Sequence
Embedded Program algorithm in progress
Data Poll from System
The Program Suspend command allows the system to interrupt a programming operation or a Write to Buffer programming operation so that data can be read from any non-suspended sector. When the Program Suspend command is written during a programming process, the device halts the program operation within 15 s max (5 s typical) and updates the status bits. Addresses are not required when writing the Program Suspend command. After the programming operation has been suspended, the system can read array data from any non-suspended sector. The Program Suspend command may also be issued during a programming operation while an erase is suspended. In this case, data may be read from any addresses not in Erase Suspend or Program Suspend. If a read is needed from the SecSi Sector area (One-time Program area), then user must use the proper command sequences to enter and exit this region. The system may also write the autoselect command sequence when the device is in the Program Suspend mode. The system can read as many autoselect codes as required. When the device exits the autoselect mode, the device reverts to the Program Suspend mode, and is ready for another valid operation. See Autoselect Command Sequence for more information. After the Program Resume command is written, the device reverts to programming. The system can determine the status of the program operation using the DQ7 and DQ15 or DQ6 and DQ14 status bits, just as in the standard program operation. See Write Operation Status for more information. The system must write the Program Resume command (address bits are don't care) to exit the Program Suspend mode and continue the programming operation. Further writes of the Resume command are ignored. Another Program Suspend command can be written after the device has resume programming.
Verify Data?
No
Yes No
Increment Address
Last Address?
Yes Programming Completed
Note: See Tables 10 and 11 for program command sequence.
Figure 5.
Program Operation
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PRELIMINARY When the Embedded Erase algorithm is complete, the device returns to the read mode and addresses are no longer latched. The system can determine the status of the erase operation by using DQ7 and DQ15, DQ6 and DQ14, or DQ2 and DQ10. Refer to the Write Operation Status section for information on these status bits. Any commands written during the chip erase operation are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the chip erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity.Note that the SecSi Sector, autoselect, and CFI functions are unavailable when an erase operation in is progress. Figure illustrates the algorithm for the erase operation. Refer to the Erase and Program Operations tables in the AC Characteristics section for parameters, and Figure 18 section for timing diagrams.
Write Program Resume Command Sequence
Program Operation or Write-to-Buffer Sequence in Progress
Write address/data XXXh/B0h
Write Program Suspend Command Sequence Command is also valid for Erase-suspended-program operations
Wait 15 s
Read data as required
Autoselect and SecSi Sector read operations are also allowed Data cannot be read from erase- or program-suspended sectors
No
Done reading? Yes Write address/data XXXh/30h
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock cycles are written, and are then followed by the address of the sector to be erased, and the sector erase command. Table 11 shows the address and data requirements for the sector erase command sequence. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically programs and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. After the command sequence is written, a sector erase time-out of 50 s occurs. During the time-out period, additional sector addresses and sector erase commands may be written. Loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. The time between these additional cycles must be less than 50 s, otherwise erasure may begin. Any sector erase address and command following the exceeded time-out may or may not be accepted. It is recommended that processor interrupts be disabled during this time to ensure all commands are accepted. The interrupts can be re-enabled after the last Sector Erase command is written. Any command other than Sector Erase or Erase Suspend during the time-out period resets the device to the read mode. The system must rewrite the command sequence and any additional addresses and commands. Note that the SecSi Sector, autoselect, and CFI functions are unavailable when an erase operation in is progress.
Device reverts to operation prior to Program Suspend
Figure 6.
Program Suspend/Program Resume
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the Embedded Erase algorithm. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. Tables 10 and 11 show the address and data requirements for the chip erase command sequence.
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PRELIMINARY The system can monitor DQ3 and DQ11 to determine if the sector erase timer has timed out (See the section on DQ3 and DQ11: Sector Erase Timer.). The time-out begins from the rising edge of the final WE# pulse in the command sequence. When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. Note that while the Embedded Erase operation is in progress, the system can read data from the non-erasing sector. The system can determine the status of the erase operation by reading DQ7 and DQ15, DQ6 and DQ14, or DQ2 and DQ10 in the erasing sector. Refer to the Write Operation Status section for information on these status bits. Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the sector erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. Figure illustrates the algorithm for the erase operation. Refer to the Erase and Program Operations tables in the AC Characteristics section for parameters, and Figure 18 section for timing diagrams. r
START
Write Erase Command Sequence (Notes 1, 2)
Data Poll to Erasing Bank from System
Embedded Erase algorithm in progress
No
Data = FFh?
Yes Erasure Completed
Notes: 1. See Tables 10 and 11 for program command sequence. 2. See the section on DQ3 and DQ10 for information on the sector erase timer.
Figure 7.
Erase Operation
Erase Suspend/Erase Resume Commands
The Erase Suspend command, B0h, allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. This command is valid only during the sector erase operation, including the 50 s time-out period during the sector erase command sequence. The Erase Suspend command is ignored if written during the chip erase operation or Embedded Program algorithm. When the Erase Suspend command is written during the sector erase operation, the device requires a typical of 5 s (maximum of 20 s) to suspend the erase operation. However, when the Erase Suspend command is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation. After the erase operation has been suspended, the device enters the erase-suspend-read mode. The system can read data from or program data to any sector not selected for erasure. (The device "erase suspends" all sectors selected for erasure.) Reading at any address within erase-suspended sectors pro-
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PRELIMINARY duces status information on DQ15-DQ0. The system can use DQ7 and DQ15, or DQ6 and DQ14 and DQ2 and DQ10 together, to determine if a sector is actively erasing or is erase-suspended. Refer to the Write Operation Status section for information on these status bits. After an erase-suspended program operation is complete, the device returns to the erase-suspend-read mode. The system can determine the status of the program operation using the DQ7 and DQ15 or DQ6 and DQ14 status bits, just as in the standard word program operation. Refer to the Write Operation Status section for more information. In the erase-suspend-read mode, the system can also issue the autoselect command sequence. Refer to the Autoselect Mode and Autoselect Command Sequence sections for details. To resume the sector erase operation, the system must write the Erase Resume command. Fur ther writes of the Resume command are ignored. Another Erase Suspend command can be written after the chip has resumed erasing.
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PRELIMINARY
Command Definitions
Table 10.
Command Sequence (Note 1) Read (Note 6) Reset (Note 7) Autoselect (Note 8) Manufacturer ID Device ID (Note 9) SecSiTM Sector Factory Protect (Note 10) Sector Group Protect Verify (Note 12) Cycles
Command Definitions (x32 Mode, WORD# = VIH)
Bus Cycles (Notes 2-5) First Second Addr Data Third Addr Data Fourth Addr Data Fifth Addr Data Sixth Addr Data
Addr RA XXX 555 555 555 555 555 555 555 555 SA 555 555 XXX XXX 555 555 XXX XXX 55
Data RD F0F0 AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA 2929 AAAA AAAA A0A0 9090 AAAA AAAA B0B0 3030 9898
1 1 4 6 4 4 3 4 4 3 1 3 3 2 2 6 6 1 1 1
2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA PA XXX 2AA 2AA
5555 5555 5555 5555 5555 5555 5555 5555 5555 5555 PD 0000 5555 5555
555 555 555 555 555 555 555 SA 555 555
9090 9090 9090
X00 X01 X03
00000101 22227 E7E (Note 10) 0000/ 0101 0000 PD DWC PA PD WBL PD X0E 2222 1212 X0F 2222 0101
9090 (SA)X02 8888 9090 A0A0 2525 F0F0 2020 XXX PA SA
Enter SecSi Sector Region Exit SecSi Sector Region Program Write to Buffer (Note 11) Program Buffer to Flash Write to Buffer Abort Reset (Note 13) Unlock Bypass Unlock Bypass Program (Note 14) Unlock Bypass Reset (Note 15) Chip Erase Sector Erase Program/Erase Suspend (Note 16) Program/Erase Resume (Note 17) CFI Query (Note 18)
555 555
8080 8080
555 555
AAAA AAAA
2AA 2AA
5555 5555
555 SA
1010 3030
Legend: X = Don't care RA = Read Address of the memory location to be read. RD = Read Data read from location RA during read operation. PA = Program Address. Addresses latch on the falling edge of the WE# or CE# pulse, whichever happens later. PD = Program Data for location PA. Data latches on the rising edge of WE# or CE# pulse, whichever happens first. Notes:
1. See Table 1 for description of bus operations.
SA = Sector Address of sector to be verified (in autoselect mode) or erased. Address bits A23-A15 uniquely select any sector. WBL = Write Buffer Location. Address must be within the same write buffer page as PA. DWC = Doubleword Count. Number of write buffer locations to load minus 1.
2. 3. 4. 5. 6. 7.
All values are in hexadecimal. Except for the read cycle and the fourth cycle of the autoselect command sequence, all bus cycles are write cycles. Data bits DQ31-DQ16 are don't care in command sequences, except for RD, PD and DWC. Unless otherwise noted, address bits A23-A11 are don't cares. No unlock or command cycles required when device is in read mode. The Reset command is required to return to the read mode (or to the erase-suspend-read mode if previously in Erase Suspend) when the device is in the autoselect mode, or if DQ5 and/or DQ13 goes high while the device is providing status information. The fourth cycle of the autoselect command sequence is a read cycle. Data bits DQ31-DQ16 are don't care. See the Autoselect Command Sequence section for more information. The device ID must be read in three cycles.
11. The total number of cycles in the command sequence is determined by the number of doublewords written to the write buffer. The maximum number of cycles in the command sequence is 21. 12. The data is 0000h for an unprotected sector and 0101h for a protected sector. 13. Command sequence resets device for next command after aborted write-to-buffer operation. 14. The Unlock Bypass command is required prior to the Unlock Bypass Program command. 15. The Unlock Bypass Reset command is required to return to the read mode when the device is in the unlock bypass mode. 16. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspend command is valid only during a sector erase operation. 17. The Erase Resume command is valid only during the Erase Suspend mode.
18. Command is valid when device is ready to read array data or when device is in autoselect mode.
8.
9.
10. If WP# protects the highest address sector, the data is 9898h for factory locked and 1818h for not factory locked. If WP# protects the lowest address sector, the data is 8888h for factory locked and 0808h for not factor locked.
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PRELIMINARY Table 11.
Command Sequence (Note 1) Read (Note 6) Reset (Note 7) Autoselect (Note 8) Manufacturer ID Device ID (Note 9) SecSiTM Sector Factory Protect (Note 10) Sector Group Protect Verify (Note 12) Cycles
Command Definitions (x16 Mode, WORD# = VIL)
Bus Cycles (Notes 2-5) First Second Addr Data Third Addr Data Fourth Addr Data Fifth Addr Data Sixth Addr Data
Addr RA XXX AAA AAA AAA AAA AAA AAA AAA AAA SA AAA AAA XXX XXX AAA AAA XXX XXX AA
Data RD F0F0 AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA 2929 AAAA AAAA A0A0 9090 AAAA AAAA B0B0 3030 9898
1 1 4 6 4 4 3 4 4 3 1 3 3 2 2 6 6 1 1 1
555 555 555 555 555 555 555 555 555 555 PA XXX 555 555
5555 5555 5555 5555 5555 5555 5555 5555 5555 5555 PD 0000 5555 5555
AAA AAA AAA AAA AAA AAA AAA SA AAA AAA
9090 9090 9090
X00 X02 X06
0101 7E7E (Note 10) 0000/ 0101 0000 PD WC PA PD WBL PD X1C 1212 X1E 0101
9090 (SA)X04 8888 9090 A0A0 2525 F0F0 2020 XXX PA SA
Enter SecSi Sector Region Exit SecSi Sector Region Program Write to Buffer (Note 11) Program Buffer to Flash Write to Buffer Abort Reset (Note 13) Unlock Bypass Unlock Bypass Program (Note 14) Unlock Bypass Reset (Note 15) Chip Erase Sector Erase Program/Erase Suspend (Note 16) Program/Erase Resume (Note 17) CFI Query (Note 18)
AAA AAA
8080 8080
AAA AAA
AAAA AAAA
555 555
5555 5555
AAA SA
1010 3030
Legend: X = Don't care RA = Read Address of the memory location to be read. RD = Read Data read from location RA during read operation. PA = Program Address. Addresses latch on the falling edge of the WE# or CE# pulse, whichever happens later. PD = Program Data for location PA. Data latches on the rising edge of WE# or CE# pulse, whichever happens first. Notes:
1. See Table 1 for description of bus operations.
SA = Sector Address of sector to be verified (in autoselect mode) or erased. Address bits A23-A15 uniquely select any sector. WBL = Write Buffer Location. Address must be within the same write buffer page as PA. WC = Word Count. Number of write buffer locations to load minus 1.
2. 3. 4. 5. 6. 7.
All values are in hexadecimal. Except for the read cycle and the fourth cycle of the autoselect command sequence, all bus cycles are write cycles. Data bits DQ31-DQ15 are don't care in command sequences. Unless otherwise noted, address bits A23-A11 are don't cares. No unlock or command cycles required when device is in read mode. The Reset command is required to return to the read mode (or to the erase-suspend-read mode if previously in Erase Suspend) when the device is in the autoselect mode, or if DQ5 and/or DQ13goes high while the device is providing status information. The fourth cycle of the autoselect command sequence is a read cycle. Data bits DQ31-DQ16 are don't care. See the Autoselect Command Sequence section for more information. The device ID must be read in three cycles.
11. The total number of cycles in the command sequence is determined by the number of words written to the write buffer. The maximum number of cycles in the command sequence is 37. 12. The data is 0000h for an unprotected sector group and 0101h for a protected sector group. 13. Command sequence resets device for next command after aborted write-to-buffer operation. 14. The Unlock Bypass command is required prior to the Unlock Bypass Program command. 15. The Unlock Bypass Reset command is required to return to the read mode when the device is in the unlock bypass mode. 16. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspend command is valid only during a sector erase operation. 17. The Erase Resume command is valid only during the Erase Suspend mode.
18. Command is valid when device is ready to read array data or when device is in autoselect mode.
8.
9.
10. If WP# protects the highest address sector, the data is 9898h for factory locked and 1818h for not factory locked. If WP# protects the lowest address sector, the data is 8888h for factory locked and 0808h for not factor locked.
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PRELIMINARY
WRITE OPERATION STATUS
The device provides several bits to determine the status of a program or erase operation: DQ2 and DQ10, DQ3 and DQ11, DQ5 and DQ13, DQ6 and DQ14, and DQ7 and DQ15. Table 12 and the following subsections describe the function of these bits. DQ7 and DQ15 and DQ6 and DQ14 each offer a method for determining whether a program or erase operation is complete or in progress. The device also provides a hardware-based output signal, RY/BY#, to determine whether an Embedded Program or Erase operation is in progress or has been completed. pleted the program or erase operation and DQ7 has valid data, the data outputs on DQ6-DQ0 and D Q1 4-D Q8 may be s ti ll i nva lid . Val id d ata o n DQ15-DQ0 will appear on successive read cycles. Table 12 shows the outputs for Data# Polling on DQ7 and DQ15. Figure 7 shows the Data# Polling algorithm. Figure 19 in the AC Characteristics section shows the Data# Polling timing diagram.
DQ7 and DQ5: Data# Polling
The Data# Polling bit, DQ7 and DQ15, indicates to the host system whether an Embedded Program or Erase algorithm is in progress or completed, or whether the device is in Erase Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the command sequence. During the Embedded Program algorithm, the device outputs on DQ7 and DQ15 the complement of the datum programmed to DQ7 and DQ15. This DQ7 and DQ15 status also applies to programming during Erase Suspend. When the Embedded Program algorithm is complete, the device outputs the datum programmed to DQ7 and DQ15. The system must provide the program address to read valid status information on DQ7 and DQ15. If a program address falls within a protected sector, Data# Polling on DQ7 and DQ15 is active for approximately 1 s, then the device returns to the read mode. During the Embedded Erase algorithm, Data# Polling produces a "0" on DQ7 and DQ15. When the Embedded Erase algorithm is complete, or if the device enters the Erase Suspend mode, Data# Polling produces a "1" on DQ7 and DQ15. The system must provide an address within any of the sectors selected for erasure to read valid status information on DQ7 and DQ15. After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling on DQ7 and DQ15 is active for approximately 100 s, then the device returns to the read mode. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. However, if the system reads DQ7 and DQ15 at an address within a protected sector, the status may not be valid. Just prior to the completion of an Embedded Program or Erase operation, DQ7 and DQ15 may change asynchronously with DQ6-DQ0 and DQ14-DQ8 while Output Enable (OE#) is asserted low. That is, the device may change from providing status information to valid data on DQ7 and DQ15. Depending on when the system samples the DQ7 and DQ15 output, it may read the status or valid data. Even if the device has com-
START
Read DQ7-DQ0 Addr = VA
DQ7 = Data?
Yes
No No
DQ5 = 1?
Yes Read DQ7-DQ0 Addr = VA
DQ7 = Data?
Yes
No FAIL PASS
Notes: 1. VA = Valid address for programming. During a sector erase operation, a valid address is any sector address within the sector being erased. During chip erase, a valid address is any non-protected sector address.
2. DQ7 and DQ15 should be rechecked even if DQ5 and/or DQ13 = "1" because DQ7 and DQ15 may change simultaneously with DQ5 and DQ13.
Figure 7. Data# Polling Algorithm
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PRELIMINARY
RY/BY#: Ready/Busy#
The RY/BY# is a dedicated, open-drain output pin which indicates whether an Embedded Algorithm is in progress or complete. The RY/BY# status is valid after the rising edge of the final WE# pulse in the command sequence. Since RY/BY# is an open-drain output, several RY/BY# pins can be tied together in parallel with a pull-up resistor to VCC. If the output is low (Busy), the device is actively erasing or programming. (This includes programming in the Erase Suspend mode.) If the output is high (Ready), the device is in the read mode, the standby mode, or in the erase-suspend-read mode. Table 12 shows the outputs for RY/BY#.
After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 and DQ14 toggles for approximately 100 s, then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. The system can use DQ6 and DQ14 and DQ2 and DQ10 together to determine whether a sector is actively erasing or is erase-suspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6 and DQ14 toggle. When the device enters the Erase Suspend mode, DQ6 and DQ14 stop toggling. However, the system must also use DQ2 and DQ10 to determine which sectors are erasing or erase-suspended. Alternatively, the system can use DQ7 and DQ15 (see the subsection on DQ7 and DQ15: Data# Polling). If a program address falls within a protected sector, DQ6 and DQ14 toggle for approximately 1 s after the program command sequence is written, then returns to reading array data. DQ6 and DQ14 also toggle during the erase-suspend-program mode, and stops toggling once the Embedded Program algorithm is complete. Table 12 shows the outputs for Toggle Bit I on DQ6 and DQ14. Figure 8 shows the toggle bit algorithm. Figure 20 in the "AC Characteristics" section shows the toggle bit timing diagrams. Figure 21 shows the differences between DQ2 and DQ10 and DQ6 and DQ14 in graphical form. See also the subsection on DQ2 and DQ10: Toggle Bits II.
DQ6 and DQ14: Toggle Bits I
Toggle Bit I on DQ6 and DQ14indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge of the final WE# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause DQ6 and DQ14 to toggle. The system may use either OE# or CE# to control the read cycles. When the operation is complete, DQ6 and DQ14 stops toggling.
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Am29LV2562M
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PRELIMINARY
DQ2 and DQ10: Toggle Bits II
START
Read DQ7-DQ0
The "Toggle Bits II" on DQ2 and DQ10, when used with DQ6 and DQ14, indicate whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bits II are valid after the rising edge of the final WE# pulse in the command sequence. DQ2 and DQ10 toggle when the system reads at addresses within those sectors that have been selected for erasure. (The system may use either OE# or CE# to control the read cycles.) But DQ2 and DQ10 cannot distinguish whether the sector is actively erasing or is erase-suspended. DQ6 and DQ14, by comparison, indicate whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sector and mode information. Refer to Table 12 to compare outputs for DQ2 and DQ10 and DQ6 and DQ14. Figure 8 shows the toggle bit algorithm in flowchart form, and the section "DQ2 and DQ10: Toggle Bits II" explains the algor ithm. See al so the RY/B Y#: Ready/Busy# subsection. Figure 20 shows the toggle bit timing diagram. Figure 21 shows the differences between DQ2 and DQ10 and DQ6 and DQ14 in graphical form.
Read DQ7-DQ0
Toggle Bit = Toggle? Yes
No
No
DQ5 = 1?
Yes
Read DQ7-DQ0 Twice
Toggle Bit = Toggle?
No
Reading Toggle Bits DQ6 and DQ14/DQ2 and DQ10
Refer to Figure 8 for the following discussion. Whenever the system initially begins reading toggle bits status, it must read DQ15-DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bits are not toggling, the device has completed the program or erase operation. The system can read array data on DQ15-DQ0 on the following read cycle. However, if after the initial two read cycles, the system determines that one of the toggle bits are still toggling, the system also should note whether the value of DQ5 and DQ13 is high (see the section on DQ5 and DQ13). If it is, the system should then deter mine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 and/or DQ13 went high. If the toggle bits are no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not completed the operation successfully, and the system must write the reset command to return to reading array data.
Yes Program/Erase Operation Not Complete, Write Reset Command Program/Erase Operation Complete
Note: The system should recheck the toggle bit even if DQ5 and DQ13= "1" because the toggle bit may stop toggling as DQ5 and DQ13 changes to "1." See the subsections on DQ6 and DQ14 and DQ2 and DQ10 for more information.
Figure 8.
Toggle Bit Algorithm
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PRELIMINARY The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 and/or DQ13 has not gone high. The system may continue to monitor the toggle bits and DQ5 and DQ13 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (top of Figure 8).
DQ3 and DQ11: Sector Erase Timer
After writing a sector erase command sequence, the system may read DQ3 and DQ11 to deter mine whether or not erasure has begun. (The sector erase timer does not apply to the chip erase command.) If additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase command. When the time-out period is complete, DQ3 and DQ11 switch from a "0" to a "1." If the time between additional sector erase commands from the system can be assumed to be less than 50 s, the system need not monitor DQ3 and DQ11. See also the Sector Erase Command Sequence section. After the sector erase command is written, the system should read the status of DQ7 and DQ15 (Data# Polling) or DQ6 and DQ14 (Toggle Bits I) to ensure that the device has accepted the command sequence, and then read DQ3 and DQ11. If DQ3 and DQ11 are "1," the Embedded Erase algorithm has begun; all further commands (except Erase Suspend) are ignored until the erase operation is complete. If DQ3 and DQ11 are "0," the device will accept additional sector erase commands. To ensure the command has been accepted, the system software should check the status of DQ3 and DQ11 prior to and following each subsequent sector erase command. If DQ3 and DQ11 are high on the second status check, the last command might not have been accepted. Table 12 shows the status of DQ3 and DQ11 relative to the other status bits.
DQ5 and DQ13: Exceeded Timing Limits
DQ5 indic ates whether the program, erase, or write-to-buffer time has exceeded a specified internal pulse count limit. Under these conditions DQ5 and DQ13 produce a "1," indicating that the program or erase cycle was not successfully completed. The device may output a "1" on DQ5 and/or DQ13 if the system tries to program a "1" to a location that was previously programmed to "0." Only an erase operation can change a "0" back to a "1." Under this condition, the device halts the operation, and when the timing limit has been exceeded, DQ5 and/or DQ13 produces a "1." In all these cases, the system must write the reset command to return the device to the reading the array (or to erase-suspend-read if the device was previously in the erase-suspend-program mode).
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DQ1: Write-to-Buffer Abort
DQ1 indicates whether a Write-to-Buffer operation was aborted. Under these conditions DQ1 and DQ9 produce a "1". The system must issue the
Write-to-Buffer-Abort-Reset command sequence to return the device to reading array data. See Write Buffer Programming section for more details.
Table 12.
Write Operation Status
DQ5/ DA13 (Note 1) 0 0 DQ3/ DQ11 N/A 1 DQ2/DQ10 (Note 2) No toggle Toggle DQ1/ DQ9 0 N/A
Standard Mode Program Suspend Mode
Erase Suspend Mode
Write-toBuffer
Status Embedded Program Algorithm Embedded Erase Algorithm Program-Suspended ProgramSector Suspend Non-Program Read Suspended Sector Erase-Suspended 1 EraseSector Suspend Non-Erase Read Suspended Sector Erase-Suspend-Program DQ7/DQ15# (Embedded Program) Busy (Note 3) DQ7/DQ15# Abort (Note 4) DQ7/DQ15#
DQ7/DQ15 (Note 2) DQ6/DQ14 DQ7/DA15# Toggle 0 Toggle
RY/BY# 0 0 1 1
Invalid (not allowed) Data No toggle 0 Data Toggle Toggle Toggle 0 0 0 N/A N/A N/A N/A N/A N/A N/A 0 1 N/A Toggle N/A
1 1 0 0 0
Notes: 1. DQ5 and DQ13 switch to `1' when an Embedded Program, Embedded Erase, or Write-to-Buffer operation has exceeded the maximum timing limits. Refer to the section on DQ5 and DQ13 for more information.
2. DQ7 and DQ15 and DQ2 and DQ10 require a valid address when reading status information. Refer to the appropriate subsection for further details. 3. The Data# Polling algorithm should be used to monitor the last loaded write-buffer address location. 4. DQ1 and DQ9 switch to `1' when the device has aborted the write-to-buffer operation.
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PRELIMINARY
ABSOLUTE MAXIMUM RATINGS
Storage Temperature Plastic Packages . . . . . . . . . . . . . . . -65C to +150C Ambient Temperature with Power Applied. . . . . . . . . . . . . . -65C to +125C Voltage with Respect to Ground VCC (Note 1) . . . . . . . . . . . . . . . . .-0.5 V to +4.0 V A9, OE#, WP#/ACC, and RESET# (Note 2) . . . . . . . . . . . . . . . . . . . .-0.5 V to +12.5 V All other pins (Note 1) . . . . . . -0.5 V to VCC +0.5 V Output Short Circuit Current (Note 3) . . . . . . 200 mA
Notes: 1. Minimum DC voltage on input or I/O pins is -0.5 V. During voltage transitions, input or I/O pins may overshoot V SS to -2.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is VCC +0.5 V. See Figure 9. During voltage transitions, input or I/O pins may overshoot to VCC +2.0 V for periods up to 20 ns. See Figure 10.
2. Minimum DC input voltage on pins A9, OE#, ACC, and RESET# is -0.5 V. During voltage transitions, A9, OE#, WP#/ACC, and RESET# may overshoot VSS to -2.0 V for periods of up to 20 ns. See Figure 9. Maximum DC input voltage on pin A9, OE#, WP#/ACC, and RESET# is +12.5 V which may overshoot to +14.0 V for periods up to 20 ns. 3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second. Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. +0.8 V -0.5 V -2.0 V 20 ns 20 ns 20 ns
Figure 9. Maximum Negative Overshoot Waveform
20 ns VCC +2.0 V VCC +0.5 V 2.0 V 20 ns 20 ns
Figure 10. Maximum Positive Overshoot Waveform
OPERATING RANGES
Industrial (I) Devices Ambient Temperature (TA) . . . . . . . . . -40C to +85C Supply Voltages VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0-3.6 V VIO (Note 5) . . . . . . . . . . . . . . . . . . . . . . . . . 1.65-3.6 V
4. Operating ranges define those limits between which the functionality of the device is guaranteed. 5. The I/Os will not operate at 3 V when VIO = 1.8 V
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DC CHARACTERISTICS CMOS Compatible
Parameter Symbol ILI ILIT ILO ILR Parameter Description (Notes) Input Load Current (1) A9, ACC Input Load Current Output Leakage Current Reset Leakage Current Test Conditions VIN = VSS to VCC, VCC = VCC max VCC = VCC max; A9 = 12.5 V VOUT = VSS to VCC, VCC = VCC max VCC = VCC max; RESET# = 12.5 V 1 MHz ICC1 VCC Active Read Current (2, 3) CE# = VIL, OE# = VIH, 5 MHz 1 MHz ICC2 ICC3 ICC4 ICC5 ICC6 ICC7 VIL1 VIH1 VIL2 VIH2 VHH VID VOH1 VOH2 VLKO Low VCC Lock-Out Voltage (9) 10 MHz VCC Initial Page Read Current (2, 3) VCC Intra-Page Read Current (2, 3) VCC Active Write Current (3, 4) VCC Standby Current (3) VCC Reset Current (3) Automatic Sleep Mode (3, 5) Input Low Voltage 1(6, 7) Input High Voltage 1 (6, 7) Input Low Voltage 2 (6, 8) Input High Voltage 2 (6, 8) Voltage for ACC Program Acceleration Voltage for Autoselect and Temporary Sector Unprotect Output High Voltage VCC = 2.7 -3.6 V VCC = 2.7 -3.6 V IOH = -2.0 mA, VCC = VCC min = VIO IOH = -100 A, VCC = VCC min = VIO CE# = VIL, OE# = VIH CE# = VIL, OE# = VIH CE# = VIL, OE# = VIH CE#, RESET# = VCC 0.3 V, WP# = VIH RESET# = VSS 0.3 V, WP# = VIH VIH = VCC 0.3 V; VIL = VSS 0.3 V, WP# = VIH -0.5 1.9 -0.5 1.9 11.5 11.5 0.85 VIO VIO-0.4 2.3 2.5 10 MHz 33 MHz 6 26 8 80 6 12 100 2 2 2 Min Typ Max 2.0 70 2.0 35 68 mA 86 100 160 40 80 120 10 10 10 0.8 VCC + 0.5 0.3 x VIO VIO + 0.5 12.5 12.5 mA mA mA mA mA A A A V V V V V V V V V Unit A A A A
Notes:
1. On the WP#/ACC pin only, the maximum input load current when WP# = VIL is 5.0 A.
5. 6. 7. 8.
9.
Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. If VIO < VCC, maximum VIL for CE# and DQ I/Os is 0.3 VIO. Maximum VIH for these connections is VIO + 0.3 V VCC voltage requirements. VIO voltage requirements. Not 100% tested
2. 3. 4.
The ICC current listed is typically less than 4 mA/MHz, with OE# at VIH. Maximum ICC specifications are tested with VCC = VCCmax. ICC active while Embedded Erase or Embedded Program is in progress.
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TEST CONDITIONS
Table 13.
3.3 V Test Condition Output Load Output Load Capacitance, CL (including jig capacitance) CL 6.2 k Input Rise and Fall Times Input Pulse Levels Input timing measurement reference levels (See Note) Output timing measurement reference levels
Test Specifications
All Speeds 1 TTL gate 30 5 0.0-3.0 1.5 0.5 VCC pF ns V V V Unit
Device Under Test
2.7 k
Note: Diodes are IN3064 or equivalent.
Figure 11.
Test Setup
KEY TO SWITCHING WAVEFORMS
WAVEFORM INPUTS Steady Changing from H to L Changing from L to H Don't Care, Any Change Permitted Does Not Apply Changing, State Unknown Center Line is High Impedance State (High Z) OUTPUTS
3.0 V 0.0 V
Input
1.5 V
Measurement Level
0.5 VIO V
Output
Figure 12. Input Waveforms and Measurement Levels
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AC CHARACTERISTICS Read-Only Operations
Parameter JEDEC tAVAV tAVQV tELQV Std. tRC tACC tCE Description Read Cycle Time (Note 1) Address to Output Delay Chip Enable to Output Delay CE#, OE# = VIL OE# = VIL Test Setup Min Max Max Max Max Max Max Min Min Min Speed Options 120R 120 120 120 30 30 25 25 0 0 10 Unit ns ns ns ns ns ns ns ns ns ns
tPACC Page Access Time tGLQV tEHQZ tGHQZ tAXQX tOE tDF tDF tOH Output Enable to Output Delay Chip Enable to Output High Z (Note 1) Output Enable to Output High Z (Note 1) Output Hold Time From Addresses, CE# or OE#, Whichever Occurs First Read tOEH Output Enable Hold Time (Note 1) Toggle and Data# Polling
Notes: 1. Not 100% tested. 2. See Figure 11 and Table 13 for test specifications. 3. AC specifications listed are tested with VIO = VCC. Contact AMD for information on AC operation when VIO VCC.
tRC Addresses CE# tRH tRH OE# tOEH WE# HIGH Z Outputs RESET# RY/BY# Output Valid tCE tOH HIGH Z tOE tDF Addresses Stable tACC
0V
Figure 13.
Read Operation Timings
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PRELIMINARY
AC CHARACTERISTICS
A23-A2 Same Page
A1-A0*
Aa
tACC
Ab
tPACC
Ac
tPACC tPACC
Ad
Data Bus CE# OE#
Qa
Qb
Qc
Qd
* Figure shows doubleword mode. Addresses are A1-A-1 for word mode.
Figure 14.
Page Read Timings
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AC CHARACTERISTICS Hardware Reset (RESET#)
Parameter JEDEC Std. tReady tReady tRP tRH tRPD Description RESET# Pin Low (During Embedded Algorithms) to Read Mode (See Note) RESET# Pin Low (NOT During Embedded Algorithms) to Read Mode (See Note) RESET# Pulse Width Reset High Time Before Read (See Note) RESET# Low to Standby Mode Max Max Min Min Min All Speed Options 20 500 500 50 20 Unit s ns ns ns s
Note:
1. Not 100% tested. 2. AC specifications listed are tested with VIO = VCC. Contact AMD for information on AC operation when VIO VCC
RY/BY#
CE#, OE# tRH RESET# tRP tReady
Reset Timings NOT during Embedded Algorithms Reset Timings during Embedded Algorithms
tReady RY/BY# tRB CE#, OE#
RESET# tRP
Figure 15.
Reset Timings
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PRELIMINARY
AC CHARACTERISTICS Erase and Program Operations
Parameter JEDEC tAVAV tAVWL Std. tWC tAS tASO tWLAX tAH tAHT tDVWH tWHDX tDS tDH tOEPH tGHWL tELWL tWHEH tWLWH tWHDL tGHWL tCS tCH tWP tWPH Description Write Cycle Time (Note 1) Address Setup Time Address Setup Time to OE# low during toggle bit polling Address Hold Time Address Hold Time From CE# or OE# high during toggle bit polling Data Setup Time Data Hold Time Output Enable High during toggle bit polling Read Recovery Time Before Write (OE# High to WE# Low) CE# Setup Time CE# Hold Time Write Pulse Width Write Pulse Width High Write Buffer Program Operation (Notes 2, 3) Effective Write Buffer Program Operation (Notes 2, 4) Accelerated Effective Write Buffer Program Operation (Notes 2, 4) Single Doubleword/Word Program Operation (Note 2) Accelerated Single Doubleword/Word Programming Operation (Note 2) tWHWH2 tWHWH2 tVHH tVCS Sector Erase Operation (Note 2) VHH Rise and Fall Time (Note 1) VCC Setup Time (Note 1) Per Word Per Doubleword Per Word Per Doubleword Word Doubleword Word Doubleword Min Min Min Min Min Min Min Min Min Min Min Min Min Typ Typ Typ Typ Typ Typ Typ Typ Typ Typ Min Min 120R 120 0 15 45 0 45 0 20 0 0 0 35 30 240 7.5 15 6.25 12.5 60 60 54 54 0.5 250 50 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns s s s s s s s s s sec ns s
tWHWH1
tWHWH1
Notes: 1. Not 100% tested. 2. See the "Erase And Programming Performance" section for more information. 3. For 1-16 doublewords/1-32 words programmed. 4. Effective write buffer specification is based upon a 16-doubleword/32-word write buffer operation. 5. AC specifications listed are tested with VIO = VCC. Contact AMD for information on AC operation when VIO VCC
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AC CHARACTERISTICS
Program Command Sequence (last two cycles) tWC Addresses 555h tAS PA tAH CE# OE# tWP WE# tCS tDS Data tDH PD tBUSY RY/BY# Status DOUT tRB tWPH tWHWH1 PA PA Read Status Data (last two cycles)
tCH
A0h
VCC tVCS
Notes: 1. PA = program address, PD = program data, DOUT is the true data at the program address. 2. Illustration shows device in word mode.
Figure 16.
Program Operation Timings
VHH
ACC
VIL or VIH tVHH tVHH
VIL or VIH
Figure 17.
Accelerated Program Timing Diagram
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PRELIMINARY
AC CHARACTERISTICS
Erase Command Sequence (last two cycles) tWC Addresses 2AAh tAS SA
555h for chip erase
Read Status Data
VA tAH
VA
CE#
OE# tWP WE# tCS tDS
tCH
tWPH
tWHWH2
tDH Data 55h 30h
10 for Chip Erase In Progress Complete
tBUSY RY/BY# tVCS VCC
tRB
Notes: 1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see "Write Operation Status"). 2. These waveforms are for the doubleword mode.
Figure 18.
Chip/Sector Erase Operation Timings
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AC CHARACTERISTICS
tRC Addresses VA tACC tCE CE# tCH OE# tOEH WE# tOH DQ7
High Z
VA
VA
tOE tDF
Complement
Complement
True
Valid Data
High Z
DQ0-DQ6 tBUSY RY/BY#
Status Data
Status Data
True
Valid Data
Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle.
Figure 19.
Data# Polling Timings (During Embedded Algorithms)
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AC CHARACTERISTICS
tAHT Addresses tAHT tASO CE# tOEH WE# tOEPH OE# tDH DQ6/DQ2 Valid Data
Valid Status
tAS
tCEPH
tOE
Valid Status Valid Status
Valid Data
(first read) RY/BY#
(second read)
(stops toggling)
Note: VA = Valid address; not required for DQ6 and DQ14. Illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle
Figure 20.
Toggle Bit Timings (During Embedded Algorithms)
Enter Embedded Erasing WE# DQ6, DQ14
Erase Suspend Erase
Enter Erase Suspend Program Erase Suspend Program
Erase Resume Erase Suspend Read Erase Erase Complete
Erase Suspend Read
DQ2, DQ10
Note: DQ2 and DQ10 toggle only when read at an address within an erase-suspended sector. The system may use OE# or CE# to toggle DQ2 and DQ1- and DQ6 and DQ14.
Figure 21.
DQ2 vs. DQ6
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PRELIMINARY
AC CHARACTERISTICS Temporary Sector Unprotect
Parameter JEDEC Std tVIDR tRSP Description VID Rise and Fall Time (See Note) RESET# Setup Time for Temporary Sector Unprotect Min Min All Speed Options 500 4 Unit ns s
Note:
1. Not 100% tested. 2. AC specifications listed are tested with VIO = VCC. Contact AMD for information on AC operation when VIO VCC
VID RESET# VSS, VIL, or VIH tVIDR Program or Erase Command Sequence CE# tVIDR
VID VSS, VIL, or VIH
WE# tRSP RY/BY# tRRB
Figure 22.
Temporary Sector Group Unprotect Timing Diagram
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PRELIMINARY
AC CHARACTERISTICS
VID VIH
RESET#
SA, A6, A1, A0
Valid* Sector Group Protect or Unprotect
Valid* Verify 40h
Sector Group Protect: 150 s, Sector Group Unprotect: 15 ms
Valid*
Data
60h
60h
Status
1 s CE#
WE#
OE#
* For sector group protect, A6 = 0, A1 = 1, A0 = 0. For sector group unprotect, A6 = 1, A1 = 1, A0 = 0.
Figure 23.
Sector Group Protect and Unprotect Timing Diagram
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AC CHARACTERISTICS Alternate CE# Controlled Erase and Program Operations
Parameter JEDEC tAVAV tAVWL tELAX tDVEH tEHDX tGHEL tWLEL tEHWH tELEH tEHEL Std. tWC tAS tAH tDS tDH tGHEL tWS tWH tCP tCPH Description Write Cycle Time (Note 1) Address Setup Time Address Hold Time Data Setup Time Data Hold Time Read Recovery Time Before Write (OE# High to WE# Low) WE# Setup Time WE# Hold Time CE# Pulse Width CE# Pulse Width High Write Buffer Program Operation (Notes 2, 3) Effective Write Buffer Program Operation (Notes 2, 4) Effective Accelerated Write Buffer Program Operation (Notes 2, 4) Program Operation (Note 2) Doubleword Accelerated Programming Operation (Note 2) tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Word Doubleword Typ Typ Typ Typ 60 54 54 0.5 s s s sec Per Word Per Doubleword Per Word Per Doubleword Word Min Min Min Min Min Min Min Min Min Min Typ Typ Typ Typ Typ Typ 120R 120 0 45 45 0 0 0 0 45 30 240 7.5 15 6.25 12.5 60 Unit ns ns ns ns ns ns ns ns ns ns s s s s s s
tWHWH1
tWHWH1
Notes: 1. Not 100% tested. 2. See the "Erase And Programming Performance" section for more information. 3. For 1-16 doublewords/1-32 words programmed. 4. Effective write buffer specification is based upon a 16-doubleword/32-word write buffer operation. 5. AC specifications listed are tested with VIO = VCC. Contact AMD for information on AC operation when VIO VCC.
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PRELIMINARY
AC CHARACTERISTICS
555 for program 2AA for erase PA for program SA for sector erase 555 for chip erase
Data# Polling PA
Addresses tWC tWH WE# tGHEL OE# tCP CE# tWS tCPH tDS tDH Data tRH
A0 for program 55 for erase PD for program 30 for sector erase 10 for chip erase
tAS tAH
tWHWH1 or 2
tBUSY
DQ7#
DOUT
RESET#
RY/BY#
Notes: 1. Figure indicates last two bus cycles of a program or erase operation. 2. PA = program address, SA = sector address, PD = program data. 3. DQ7# and DQ15# are the complement of the data written to the device. DOUT is the data written to the device. 4. Waveforms are for the word mode.
Figure 24.
Alternate CE# Controlled Write (Erase/Program) Operation Timings
LATCHUP CHARACTERISTICS
Description Input voltage with respect to VSS on all pins except I/O pins (including A9, OE#, and RESET#) Input voltage with respect to VSS on all I/O pins VCC Current Min -1.0 V -1.0 V -100 mA Max 12.5 V VCC + 1.0 V +100 mA
Note: Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time.
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ERASE AND PROGRAMMING PERFORMANCE
Parameter Sector Erase Time Chip Erase Time Single Doubleword/Word Program Time (Note 3) Accelerated Single Doubleword/ Word Program Time Word Doubleword Word Doubleword Typ (Note 1) Max (Note 2) 0.5 256 60 60 54 54 240 Per Word Per Doubleword 7.5 15 200 6.25 12.5 252 3.5 512 600 600 540 540 1200 38 75 1040 33 65 584 Unit sec sec s s s s s s s s s s sec Excludes system level overhead (Note 6) Comments Excludes 00h programming prior to erasure (Note 5)
Total Write Buffer Program Time (Note 4) Effective Write Buffer Program Time (Note 3)
Total Accelerated Write Buffer Program Time (Note 4) Effective Write Buffer Accelerated Program Time (Note 3) Chip Program Time Per Word Per Doubleword
Notes: 1. Typical program and erase times assume the following conditions: 25C, 3.0 V VCC, 10,000 cycles. Additionally, programming typicals assume checkerboard pattern. 2. Under worst case conditions of 90C, VCC = 3.0 V, 100,000 cycles. 3. Effective write buffer specification is based upon a 16-doubleword/32-word write buffer operation. 4. For 1-16 doublewords or 1-32 words programmed in a single write buffer programming operation. 5. In the pre-programming step of the Embedded Erase algorithm, all bits are programmed to 00h before erasure. 6. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Tables 10 and 11 for further information on command definitions.
TSOP PIN AND BGA PACKAGE CAPACITANCE
Parameter Symbol CIN COUT CIN2 Parameter Description Input Capacitance Output Capacitance Control Pin Capacitance Test Setup VIN = 0 VOUT = 0 VIN = 0 BGA BGA BGA Typ TBD TBD TBD Max TBD TBD TBD Unit pF pF pF
Notes: 1. Sampled, not 100% tested. 2. Test conditions TA = 25C, f = 1.0 MHz.
DATA RETENTION
Parameter Description Minimum Pattern Data Retention Time 125C 20 Years Test Conditions 150C Min 10 Unit Years
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PHYSICAL DIMENSIONS LSC080-80-Ball Fortified Ball Grid Array 18 x 12 mm Package
D
0.20 C (2X)
8 7 6
A
D1 eD
SE
7
E eE
5 4 3 2 1
E1
INDEX MARK PIN A1 CORNER 10
K
J
H
G
F
E
D
C
B
A
B
7
TOP VIEW A A2 A1
6
0.20 C (2X) 0.25 C
SD
PIN A1 CORNER
BOTTOM VIEW
C
0.20 C
SIDE VIEW b
80X
0.25 M C A B 0.10 M C
NOTES: PACKAGE JEDEC DxE SYMBOL A A1 A2 D E D1 E1 MD ME n b eE eD SD / SE 0.50 LSC 080 N/A 18.00 mm x 12.00 mm PACKAGE MIN --0.40 1.00 NOM ------18.00 BSC. 12.00 BSC. 9.00 BSC. 7.00 BSC. 10 8 80 0.60 1.00 BSC. 1.00 BSC 0.50 BSC. 0.70 MAX 1.60 --1.11 PROFILE BALL HEIGHT BODY THICKNESS BODY SIZE BODY SIZE MATRIX FOOTPRINT MATRIX FOOTPRINT MATRIX SIZE D DIRECTION MATRIX SIZE E DIRECTION BALL COUNT BALL DIAMETER BALL PITCH BALL PITCH SOLDER BALL PLACEMENT DEPOPULATED SOLDER BALLS 9. 8. 7 6 NOTE 2. 3. 4. 5. 1. DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994. ALL DIMENSIONS ARE IN MILLIMETERS. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010. e REPRESENTS THE SOLDER BALL GRID PITCH. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME. DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. N/A
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3266 \ 16-038.15a
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PRELIMINARY
REVISION SUMMARY Revision A (November 19, 2002)
Initial release. Operating Ranges Added VCC voltage range. AC Characteristics Read-only Operations: Added note #3. Hardware Reset, Erase and Program Operations, Temporary Sector Unprotect, and Alternate CE# Controlled Erase and Program Operations Added Note.
Revision A+1 (January 22, 2003)
Distinctive Characteristics Corrected the access and page read times. Global Added Sector Group Protection throughout datasheet and added Table 4. Product Selector Guide Added VIOs to table and removed Note #2. Added regulated speed option. Connection Diagrams In the BGA package D8 is A23 and A1 is RFU. Ordering Information Corrected typos in VIO ranges. Removed Note. Added LSC080 package. SecSi Sector Flash Memory Region, and Enter SecSi Sector/Exit SecSi Sector Command Sequence Noted that the ACC function and unlock bypass modes are not available when the SecSi sector is enabled. Byte/Word Program Command Sequence, Sector Erase Command Sequence, and Chip Erase Command Sequence Noted that the SecSi Sector, autoselect, and CFI functions are unavailable when a program or erase operation is in progress. Common Flash Memory Interface (CFI) Changed wording in last sentence of third paragraph from, "...the autoselect mode." to "...reading array data." Changed CFI website address. Customer Lockable: SecSi Sector NOT Programmed or Protected at the factory. Added second bullet, SecSi sector-protect verify text and figure 3. DC Characteristics Changed V IH1 and V IH2 minimum to 1.9. Removed typos in notes. Removed VIL, V IH, VOL, and VOH from table and added VIL1 , VIH1, VIL2, V IH2, VOL, VOH1, and VOH2 from the CMOS table in the Am29LV640MH/L datasheet.
Revision A+2 (February 3, 2003)
Ordering Information Corrected OPNs.
Revision B (September 17, 2003)
Global Changed data sheet status from Advance Information to Preliminary. Distinctive Characteristics Changed description of device erase cycle endurance. Changed typical sector erase time, typical write buffer programming time, and typical active read current specification. Connection Diagrams Corrected signal name for ball D8. Erase Suspend/Erase Resume Commands Deleted reference to erase-suspended sector address requirement for commands. Tables 10 and 11, Command Definitions Corrected addresses for Erase Suspend and Erase Resume to "XXX" (don't care). DC Characteristics Changed typical and maximum values for ICC1 , ICC2 , and ICC3. Values for different frequencies were added to ICC2 and ICC3. AC Characteristics Erase and Program Operations table; Alternate CE# Controlled Erase and Program Operations table. Changed values for the following parameters: Write Buffer Program Operation, Effective Write Buffer Program Operation, Accelerated Effective Write Buffer Program Operation, Sector Erase Operation, Single Doubleword/Word Program Operation, Accelerated Single Doubleword/Word Program Operation (the phrase "Single Doubleword/Word" was added to the last two parameter titles).
October 9, 2003
Am29LV2562M
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PRELIMINARY Erase and Programming Performance Changed typical and maximum sector erase time. Changed typical values and entered maximum values for chip erase time and added maximum erase time. Replaced TBDs for all typical and maximum specifications with actual values. Added phrase "Single Doubleword/Word" to Program Time and Accelerated Program Time parameters titles. Added Total Write Buffer Program Time and Total Accelerated Write Buffer Program Time parameters to table. Changed device endurance in Note 1 to 10,000 cycles. Changed write buffer operation size in Note 3. Note 4 now refers to write buffer programming instead of chip programming. Deleted Note 7.
Revision B+1 (October 9, 2003)
Connection Diagrams Reverted entire pinout to that shown in Revision A+2. Table 1, Device Bus Operations Corrected requirement for ACC column from "X" to "L/H".
Trademarks Copyright (c) 2002-2003 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
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Am29LV2562M
October 9, 2003
Sales Offices and Representatives North America
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Representatives in Latin America
Representatives in U.S. and Canada
ARIZONA, Tempe - Centaur ............................................................(480) 839-2320 CALIFORNIA, Calabasas - Centaur ......................................................(818) 878-5800
ARGENTINA, Capital Federal. Argentina- Latin/WW Rep. ...........(+54-11) 4373-0655 CHILE, Santiago - LatinRep/WWRep. .....................................(+562) 264-0993 COLUMBIA, Bogota - Dimser.............................................................(571) 410-4182 MEXICO, Guadalajara - LatinRep/WW Rep..................................(523) 817-3900 Mexico, City - LatinRep/WW Rep..................................(525) 752-2727 Monterrey - LatinRep/WW Rep. ....................................(528) 369-6828 PUERTO RICO, Boqueron - Infitronics. ...................................................(787) 851-6000
Advanced Micro Devices reserves the right to make changes in its product without notice in order to improve design or performance characteristics. The performance characteristics listed in this document are guaranteed by specific tests, guard banding, design and other practices common to the industry. For specific testing details, contact your local AMD sales representative. The company assumes no responsibility for the use of any circuits described herein. (c) 2002 Advanced Micro Devices, Inc. One AMD Place, P.O. Box 3453, Sunnyvale, CA 94088-3453 408-732-2400 TWX 910-339-9280 TELEX 34-6306 800-538-8450 http://www.amd.com Printed in USA

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